^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD9523 SPI Low Jitter Clock Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/frequency/ad9523.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AD9523_READ (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD9523_WRITE (0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AD9523_CNT(x) (((x) - 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD9523_ADDR(x) ((x) & 0xFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AD9523_R1B (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD9523_R2B (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD9523_R3B (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD9523_TRANSF_LEN(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD9523_PART_REGISTER (AD9523_R1B | 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AD9523_READBACK_0 (AD9523_R1B | 0x22C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AD9523_READBACK_1 (AD9523_R1B | 0x22D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AD9523_IO_UPDATE (AD9523_R1B | 0x234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* AD9523_SERIAL_PORT_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AD9523_SER_CONF_SDO_ACTIVE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AD9523_SER_CONF_SOFT_RESET (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* AD9523_READBACK_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* AD9523_PLL1_CHARGE_PUMP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AD9523_PLL1_REFB_RCV_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AD9523_PLL1_REFA_RCV_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* AD9523_PLL1_REF_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* AD9523_PLL1_MISC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AD9523_PLL1_REF_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* AD9523_PLL1_LOOP_FILTER_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* AD9523_PLL2_CHARGE_PUMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* AD9523_PLL2_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* AD9523_PLL2_VCO_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AD9523_PLL2_VCO_CALIBRATE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* AD9523_PLL2_VCO_DIVIDER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* AD9523_PLL2_LOOP_FILTER_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* AD9523_PLL2_R2_DIVIDER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* AD9523_CHANNEL_CLOCK_DIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* AD9523_PLL1_OUTPUT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* AD9523_READBACK_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AD9523_READBACK_0_STAT_VCXO (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AD9523_READBACK_0_STAT_REFB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AD9523_READBACK_0_STAT_REFA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* AD9523_READBACK_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* AD9523_STATUS_SIGNALS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* AD9523_POWER_DOWN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* AD9523_IO_UPDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AD9523_IO_UPDATE_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* AD9523_EEPROM_DATA_XFER_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* AD9523_EEPROM_ERROR_READBACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* AD9523_EEPROM_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* AD9523_EEPROM_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AD9523_NUM_CHAN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AD9523_NUM_CHAN_ALT_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Helpers to avoid excess line breaks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AD9523_STAT_PLL1_LD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) AD9523_STAT_PLL2_LD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AD9523_STAT_REFA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) AD9523_STAT_REFB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) AD9523_STAT_REF_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) AD9523_STAT_VCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) AD9523_STAT_PLL2_FB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) AD9523_STAT_PLL2_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) AD9523_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AD9523_EEPROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) AD9523_VCO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) AD9523_VCO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) AD9523_VCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AD9523_NUM_CLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ad9523_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct ad9523_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct gpio_desc *pwrdown_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct gpio_desc *sync_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long vcxo_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long vco_out_freq[AD9523_NUM_CLK_SRC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Lock for accessing device registers. Some operations require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * multiple consecutive R/W operations, during which the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * shouldn't be interrupted. The buffers are also shared across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * all operations so need to be protected on stand alone reads and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } data[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* We encode the register size 1..3 bytes into the register address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * On transfer we get the size from the register datum, and make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * the result is properly aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .tx_buf = &st->data[0].d8[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .len = AD9523_TRANSF_LEN(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) st->data[0].d32 = cpu_to_be32(AD9523_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AD9523_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(&indio_dev->dev, "read failed (%d)", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (8 * (3 - AD9523_TRANSF_LEN(addr))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int ad9523_write(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int addr, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .tx_buf = &st->data[0].d8[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .len = AD9523_TRANSF_LEN(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) st->data[0].d32 = cpu_to_be32(AD9523_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AD9523_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) st->data[1].d32 = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(&indio_dev->dev, "write failed (%d)", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ad9523_io_update(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int ad9523_vco_out_map(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int ch, unsigned int out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) switch (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case 0 ... 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) out = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = ad9523_write(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case 4 ... 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case 7 ... 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = ad9523_write(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) st->vco_out_map[ch] = out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int ad9523_set_clock_provider(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int ch, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) long tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) bool use_alt_clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) switch (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 0 ... 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case 4 ... 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tmp1 = st->vco_out_freq[AD9523_VCO1] / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) tmp2 = st->vco_out_freq[AD9523_VCO2] / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tmp1 *= freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tmp2 *= freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Ch 10..14: No action required, return success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int ad9523_store_eeprom(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) AD9523_EEPROM_CTRL2_REG2EEPROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tmp = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = ad9523_read(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) AD9523_EEPROM_DATA_XFER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&indio_dev->dev, "Verify EEPROM failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int ad9523_sync(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tmp = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ad9523_io_update(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ad9523_io_update(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static ssize_t ad9523_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bool state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = strtobool(buf, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch ((u32)this_attr->address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case AD9523_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = ad9523_sync(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case AD9523_EEPROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = ad9523_store_eeprom(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static ssize_t ad9523_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = ad9523_read(indio_dev, AD9523_READBACK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = sprintf(buf, "%d\n", !!(ret & (1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (u32)this_attr->address)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) AD9523_STAT_PLL1_LD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) AD9523_STAT_PLL2_LD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) AD9523_STAT_REFA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) AD9523_STAT_REFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) AD9523_STAT_REF_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) AD9523_STAT_VCXO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) AD9523_STAT_PLL2_FB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ad9523_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) AD9523_STAT_PLL2_REF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ad9523_store,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) AD9523_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ad9523_store,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) AD9523_EEPROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct attribute *ad9523_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) &iio_dev_attr_sync_dividers.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &iio_dev_attr_store_eeprom.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) &iio_dev_attr_vcxo_clk_present.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &iio_dev_attr_pll1_locked.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) &iio_dev_attr_pll2_locked.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct attribute_group ad9523_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .attrs = ad9523_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int ad9523_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case IIO_CHAN_INFO_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *val = st->vco_out_freq[st->vco_out_map[chan->channel]] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) AD9523_CLK_DIST_DIV_REV(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case IIO_CHAN_INFO_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) AD9523_CLK_DIST_DIV_REV(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *val = code / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) *val2 = code % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int ad9523_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int ret, tmp, code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) reg |= AD9523_CLK_DIST_PWR_DOWN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case IIO_CHAN_INFO_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (val <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tmp = clamp(tmp, 1, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) reg &= ~(0x3FF << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) reg |= AD9523_CLK_DIST_DIV(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case IIO_CHAN_INFO_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) code = val * 1000000 + val2 % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) tmp = clamp(tmp, 0, 63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) reg |= AD9523_CLK_DIST_DIV_PHASE(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ad9523_io_update(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int ad9523_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned int reg, unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (readval == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ad9523_io_update(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = ad9523_read(indio_dev, reg | AD9523_R1B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *readval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const struct iio_info ad9523_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .read_raw = &ad9523_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .write_raw = &ad9523_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .debugfs_reg_access = &ad9523_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .attrs = &ad9523_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int ad9523_setup(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct ad9523_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct ad9523_platform_data *pdata = st->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct ad9523_channel_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unsigned long active_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) AD9523_SER_CONF_SOFT_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (st->spi->mode & SPI_3WIRE ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) AD9523_SER_CONF_SDO_ACTIVE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) AD9523_READBACK_CTRL_READ_BUFFERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = ad9523_io_update(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * PLL1 Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pdata->refa_r_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pdata->refb_r_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pdata->pll1_feedback_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pll1_charge_pump_current_nA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) AD9523_PLL1_BACKLASH_PW_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) AD_IF(osc_in_cmos_neg_inp_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) AD_IF(zd_in_cmos_neg_inp_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) AD_IF(zero_delay_mode_internal_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) AD9523_PLL1_ZERO_DELAY_MODE_INT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) AD9523_PLL1_REF_MODE(pdata->ref_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * PLL2 Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pll2_charge_pump_current_nA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) AD9523_PLL2_BACKLASH_CTRL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) st->vco_freq = div_u64((unsigned long long)pdata->vcxo_freq *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) (pdata->pll2_freq_doubler_en ? 2 : 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) AD9523_PLL2_FB_NDIV(pdata->pll2_ndiv_a_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pdata->pll2_ndiv_b_cnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pdata->pll2_r2_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) AD9523_PLL2_VCO_CALIBRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_div_m1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_div_m2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) AD_IFE(pll2_vco_div_m1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) AD_IFE(pll2_vco_div_m2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (pdata->pll2_vco_div_m1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) st->vco_out_freq[AD9523_VCO1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) st->vco_freq / pdata->pll2_vco_div_m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (pdata->pll2_vco_div_m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) st->vco_out_freq[AD9523_VCO2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) st->vco_freq / pdata->pll2_vco_div_m2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) AD_IF(rzero_bypass_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) for (i = 0; i < pdata->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) chan = &pdata->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (chan->channel_num < AD9523_NUM_CHAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __set_bit(chan->channel_num, &active_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = ad9523_write(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) AD9523_CHANNEL_CLOCK_DIST(chan->channel_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) AD9523_CLK_DIST_DIV(chan->channel_divider) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) (chan->sync_ignore_en ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) (chan->divider_output_invert_en ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (chan->low_power_mode_en ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) (chan->output_dis ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) AD9523_CLK_DIST_PWR_DOWN_EN : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) chan->use_alt_clock_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) st->ad9523_channels[i].type = IIO_ALTVOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) st->ad9523_channels[i].output = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) st->ad9523_channels[i].indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) st->ad9523_channels[i].channel = chan->channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) st->ad9523_channels[i].extend_name =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) chan->extended_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) st->ad9523_channels[i].info_mask_separate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) BIT(IIO_CHAN_INFO_PHASE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) BIT(IIO_CHAN_INFO_FREQUENCY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret = ad9523_write(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) AD9523_CHANNEL_CLOCK_DIST(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) AD9523_CLK_DIST_PWR_DOWN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) AD9523_STATUS_MONITOR_01_PLL12_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = ad9523_io_update(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static void ad9523_reg_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct regulator *reg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) regulator_disable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static int ad9523_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct ad9523_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct ad9523_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev_err(&spi->dev, "no platform data?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) st->reg = devm_regulator_get(&spi->dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (!IS_ERR(st->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = devm_add_action_or_reset(&spi->dev, ad9523_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (IS_ERR(st->pwrdown_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return PTR_ERR(st->pwrdown_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (IS_ERR(st->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return PTR_ERR(st->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (st->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) gpiod_direction_output(st->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) st->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (IS_ERR(st->sync_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return PTR_ERR(st->sync_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) st->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) indio_dev->info = &ad9523_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) indio_dev->channels = st->ad9523_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) indio_dev->num_channels = pdata->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = ad9523_setup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const struct spi_device_id ad9523_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {"ad9523-1", 9523},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) MODULE_DEVICE_TABLE(spi, ad9523_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static struct spi_driver ad9523_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .name = "ad9523",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .probe = ad9523_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .id_table = ad9523_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) module_spi_driver(ad9523_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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