Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) # Frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #	Direct Digital Synthesis drivers (DDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #	Clock Distribution device drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #	Phase-Locked Loop (PLL) frequency synthesizers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) # When adding new entries keep the list in alphabetical order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) menu "Frequency Synthesizers DDS/PLL"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) menu "Clock Generator/Distribution"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) config AD9523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	tristate "Analog Devices AD9523 Low Jitter Clock Generator"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	depends on SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	  Say yes here to build support for Analog Devices AD9523 Low Jitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	  Clock Generator. The driver provides direct access via sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	  To compile this driver as a module, choose M here: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	  module will be called ad9523.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # Phase-Locked Loop (PLL) frequency synthesizers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) menu "Phase-Locked Loop (PLL) frequency synthesizers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) config ADF4350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	tristate "Analog Devices ADF4350/ADF4351 Wideband Synthesizers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	depends on SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	  Say yes here to build support for Analog Devices  ADF4350/ADF4351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	  Wideband Synthesizers. The driver provides direct access via sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	  To compile this driver as a module, choose M here: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	  module will be called adf4350.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) config ADF4371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	tristate "Analog Devices ADF4371/ADF4372 Wideband Synthesizers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	depends on SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	select REGMAP_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	  Say yes here to build support for Analog Devices ADF4371 and ADF4372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	  Wideband Synthesizers. The driver provides direct access via sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	  To compile this driver as a module, choose M here: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	  module will be called adf4371.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) endmenu