Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file is part of STM32 DAC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Authors: Amelie Delaunay <amelie.delaunay@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	    Fabrice Gasnier <fabrice.gasnier@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "stm32-dac-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define STM32_DAC_CHANNEL_1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define STM32_DAC_CHANNEL_2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define STM32_DAC_IS_CHAN_1(ch)		((ch) & STM32_DAC_CHANNEL_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define STM32_DAC_AUTO_SUSPEND_DELAY_MS	2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * struct stm32_dac - private data of DAC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * @common:		reference to DAC common data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * @lock:		lock to protect against potential races when reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *			and update CR, to keep it in sync with pm_runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct stm32_dac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct stm32_dac_common *common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct mutex		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct stm32_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 en, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (STM32_DAC_IS_CHAN_1(channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		en = FIELD_GET(STM32_DAC_CR_EN1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		en = FIELD_GET(STM32_DAC_CR_EN2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return !!en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				      bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct stm32_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct device *dev = indio_dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 en = enable ? msk : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* already enabled / disabled ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	mutex_lock(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ret = stm32_dac_is_enabled(indio_dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (ret < 0 || enable == !!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		mutex_unlock(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			mutex_unlock(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mutex_unlock(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		dev_err(&indio_dev->dev, "%s failed\n", en ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			"Enable" : "Disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		goto err_put_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * When HFSEL is set, it is not allowed to write the DHRx register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * during 8 clock cycles after the ENx bit is set. It is not allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * to make software/hardware trigger during this period either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (en && dac->common->hfsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err_put_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (STM32_DAC_IS_CHAN_1(channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return ret ? ret : IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (STM32_DAC_IS_CHAN_1(channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int stm32_dac_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			      struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			      int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct stm32_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return stm32_dac_get_value(dac, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		*val = dac->common->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int stm32_dac_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			       struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			       int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct stm32_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return stm32_dac_set_value(dac, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					unsigned reg, unsigned writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					unsigned *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct stm32_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return regmap_write(dac->common->regmap, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return regmap_read(dac->common->regmap, reg, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct iio_info stm32_dac_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.read_raw = stm32_dac_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.write_raw = stm32_dac_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.debugfs_reg_access = stm32_dac_debugfs_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const char * const stm32_dac_powerdown_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	"three_state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 					const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 					unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 					uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return sprintf(buf, "%d\n", ret ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 					 uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					 const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					 const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	bool powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = strtobool(buf, &powerdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct iio_enum stm32_dac_powerdown_mode_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.items = stm32_dac_powerdown_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.get = stm32_dac_get_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.set = stm32_dac_set_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.read = stm32_dac_read_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.write = stm32_dac_write_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define STM32_DAC_CHANNEL(chan, name) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.output = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.channel = chan,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.info_mask_separate =				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		BIT(IIO_CHAN_INFO_RAW) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		BIT(IIO_CHAN_INFO_SCALE),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* scan_index is always 0 as num_channels is 1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.scan_type = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.sign = 'u',				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.realbits = 12,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.storagebits = 16,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	},						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.datasheet_name = name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.ext_info = stm32_dac_ext_info			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct iio_chan_spec stm32_dac_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct device_node *np = indio_dev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ret = of_property_read_u32(np, "reg", &channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dev_err(&indio_dev->dev, "Failed to read reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (stm32_dac_channels[i].channel == channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (i >= ARRAY_SIZE(stm32_dac_channels)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dev_err(&indio_dev->dev, "Invalid reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	indio_dev->channels = &stm32_dac_channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 * Expose only one channel here, as they can be used independently,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 * with separate trigger. Then separate IIO devices are instantiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * to manage this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	indio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int stm32_dac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct stm32_dac *dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	dac->common = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	indio_dev->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	indio_dev->info = &stm32_dac_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mutex_init(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ret = stm32_dac_chan_of_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/* Get stm32-dac-core PM online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err_pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	pm_runtime_set_suspended(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int stm32_dac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int __maybe_unused stm32_dac_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	int channel = indio_dev->channels[0].channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/* Ensure DAC is disabled before suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ret = stm32_dac_is_enabled(indio_dev, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return ret < 0 ? ret : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct dev_pm_ops stm32_dac_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	SET_SYSTEM_SLEEP_PM_OPS(stm32_dac_suspend, pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct of_device_id stm32_dac_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{ .compatible = "st,stm32-dac", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct platform_driver stm32_dac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.probe = stm32_dac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.remove = stm32_dac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		.name = "stm32-dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.of_match_table = stm32_dac_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.pm = &stm32_dac_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) module_platform_driver(stm32_dac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MODULE_ALIAS("platform:stm32-dac");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_LICENSE("GPL v2");