Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mcp4922.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Driver for Microchip Digital to Analog Converters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Supports MCP4902, MCP4912, and MCP4922.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2014 EMAC Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MCP4922_NUM_CHANNELS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) enum mcp4922_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	ID_MCP4902,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	ID_MCP4912,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	ID_MCP4922,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct mcp4922_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned int value[MCP4922_NUM_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned int vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct regulator *vref_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u8 mosi[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCP4922_CHAN(chan, bits) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.output = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.channel = chan,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.scan_type = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.sign = 'u',				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.realbits = (bits),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.storagebits = 16,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.shift = 12 - (bits),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	},						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	state->mosi[1] = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	state->mosi[0] = (addr == 0) ? 0x00 : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	state->mosi[0] |= 0x30 | ((val >> 8) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return spi_write(state->spi, state->mosi, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int mcp4922_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct mcp4922_state *state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		*val = state->value[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		*val = state->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int mcp4922_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct mcp4922_state *state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (val2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		val <<= chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		ret = mcp4922_spi_write(state, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			state->value[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct iio_chan_spec mcp4922_channels[3][MCP4922_NUM_CHANNELS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[ID_MCP4902] = { MCP4922_CHAN(0, 8),	MCP4922_CHAN(1, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[ID_MCP4912] = { MCP4922_CHAN(0, 10),	MCP4922_CHAN(1, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	[ID_MCP4922] = { MCP4922_CHAN(0, 12),	MCP4922_CHAN(1, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct iio_info mcp4922_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.read_raw = &mcp4922_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.write_raw = &mcp4922_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int mcp4922_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct mcp4922_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	const struct spi_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	state->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	state->vref_reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (IS_ERR(state->vref_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		dev_err(&spi->dev, "Vref regulator not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return PTR_ERR(state->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ret = regulator_enable(state->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		dev_err(&spi->dev, "Failed to enable vref regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = regulator_get_voltage(state->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		dev_err(&spi->dev, "Failed to read vref regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	state->vref_mv = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	indio_dev->info = &mcp4922_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	indio_dev->channels = mcp4922_channels[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	indio_dev->num_channels = MCP4922_NUM_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_err(&spi->dev, "Failed to register iio device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	regulator_disable(state->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int mcp4922_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct mcp4922_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	regulator_disable(state->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct spi_device_id mcp4922_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{"mcp4902", ID_MCP4902},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{"mcp4912", ID_MCP4912},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{"mcp4922", ID_MCP4922},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_DEVICE_TABLE(spi, mcp4922_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct spi_driver mcp4922_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		   .name = "mcp4922",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.probe = mcp4922_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.remove = mcp4922_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.id_table = mcp4922_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) module_spi_driver(mcp4922_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_AUTHOR("Michael Welling <mwelling@ieee.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_DESCRIPTION("Microchip MCP4902, MCP4912, MCP4922 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_LICENSE("GPL v2");