Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * LTC2632 Digital to analog convertors spi driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2017 Maxime Roussin-Bélanger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * expanded by Silvan Murer <silvan.murer@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define LTC2632_CMD_WRITE_INPUT_N               0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define LTC2632_CMD_UPDATE_DAC_N                0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL    0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_N      0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LTC2632_CMD_POWERDOWN_DAC_N             0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LTC2632_CMD_POWERDOWN_CHIP              0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LTC2632_CMD_INTERNAL_REFER              0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LTC2632_CMD_EXTERNAL_REFER              0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * struct ltc2632_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * @channels:		channel spec for the DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * @num_channels:	DAC channel count of the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @vref_mv:		internal reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct ltc2632_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	const size_t num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	const int vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * struct ltc2632_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @spi_dev:			pointer to the spi_device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @powerdown_cache_mask:	used to show current channel powerdown state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @vref_mv:			used reference voltage (internal or external)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @vref_reg:		regulator for the reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct ltc2632_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct spi_device *spi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int powerdown_cache_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct regulator *vref_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) enum ltc2632_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ID_LTC2632L12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	ID_LTC2632L10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ID_LTC2632L8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	ID_LTC2632H12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	ID_LTC2632H10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ID_LTC2632H8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ID_LTC2634L12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ID_LTC2634L10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ID_LTC2634L8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ID_LTC2634H12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ID_LTC2634H10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ID_LTC2634H8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ID_LTC2636L12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ID_LTC2636L10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ID_LTC2636L8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	ID_LTC2636H12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ID_LTC2636H10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ID_LTC2636H8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int ltc2632_spi_write(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			     u8 cmd, u8 addr, u16 val, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * The input shift register is 24 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * The next four are the command bits, C3 to C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * followed by the 4-bit DAC address, A3 to A0, and then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 * 12-, 10-, 8-bit data-word. The data-word comprises the 12-,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	data = (cmd << 20) | (addr << 16) | (val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	put_unaligned_be24(data, &msg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return spi_write(spi, msg, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int ltc2632_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			    int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			    int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			    long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	const struct ltc2632_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		*val = st->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int ltc2632_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			     int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			     int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			     long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct ltc2632_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (val >= (1 << chan->scan_type.realbits) || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return ltc2632_spi_write(st->spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 					 LTC2632_CMD_WRITE_INPUT_N_UPDATE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 					 chan->address, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					 chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static ssize_t ltc2632_read_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 					  uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					  const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 					  char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct ltc2632_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return sprintf(buf, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		       !!(st->powerdown_cache_mask & (1 << chan->channel)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 					   uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 					   const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					   const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					   size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	bool pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct ltc2632_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ret = strtobool(buf, &pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (pwr_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		st->powerdown_cache_mask |= (1 << chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		st->powerdown_cache_mask &= ~(1 << chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ret = ltc2632_spi_write(st->spi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				LTC2632_CMD_POWERDOWN_DAC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				chan->channel, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct iio_info ltc2632_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.write_raw	= ltc2632_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.read_raw	= ltc2632_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.read = ltc2632_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.write = ltc2632_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LTC2632_CHANNEL(_chan, _bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.channel = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.address = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			.realbits	= (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			.shift		= 16 - (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.ext_info = ltc2632_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DECLARE_LTC2632_CHANNELS(_name, _bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	const struct iio_chan_spec _name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		LTC2632_CHANNEL(0, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		LTC2632_CHANNEL(1, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		LTC2632_CHANNEL(2, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		LTC2632_CHANNEL(3, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		LTC2632_CHANNEL(4, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		LTC2632_CHANNEL(5, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		LTC2632_CHANNEL(6, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		LTC2632_CHANNEL(7, _bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static DECLARE_LTC2632_CHANNELS(ltc2632x12, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static DECLARE_LTC2632_CHANNELS(ltc2632x10, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static DECLARE_LTC2632_CHANNELS(ltc2632x8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	[ID_LTC2632L12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.channels	= ltc2632x12_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.num_channels	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	[ID_LTC2632L10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.channels	= ltc2632x10_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.num_channels	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	[ID_LTC2632L8] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.channels	= ltc2632x8_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.num_channels	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	[ID_LTC2632H12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.channels	= ltc2632x12_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.num_channels	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	[ID_LTC2632H10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.channels	= ltc2632x10_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.num_channels	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	[ID_LTC2632H8] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.channels	= ltc2632x8_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.num_channels	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	[ID_LTC2634L12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.channels	= ltc2632x12_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.num_channels	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	[ID_LTC2634L10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.channels	= ltc2632x10_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.num_channels	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	[ID_LTC2634L8] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.channels	= ltc2632x8_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.num_channels	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	[ID_LTC2634H12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.channels	= ltc2632x12_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.num_channels	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	[ID_LTC2634H10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.channels	= ltc2632x10_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.num_channels	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	[ID_LTC2634H8] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.channels	= ltc2632x8_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.num_channels	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	[ID_LTC2636L12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.channels	= ltc2632x12_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.num_channels	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	[ID_LTC2636L10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.channels	= ltc2632x10_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.num_channels	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[ID_LTC2636L8] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.channels	= ltc2632x8_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.num_channels	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.vref_mv	= 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	[ID_LTC2636H12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.channels	= ltc2632x12_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.num_channels	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	[ID_LTC2636H10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.channels	= ltc2632x10_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.num_channels	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	[ID_LTC2636H8] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.channels	= ltc2632x8_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.num_channels	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.vref_mv	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ltc2632_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct ltc2632_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct ltc2632_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	st->spi_dev = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	chip_info = (struct ltc2632_chip_info *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (PTR_ERR(st->vref_reg) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		/* use internal reference voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		st->vref_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		st->vref_mv = chip_info->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		ret = ltc2632_spi_write(spi, LTC2632_CMD_INTERNAL_REFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				"Set internal reference command failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	} else if (IS_ERR(st->vref_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				"Error getting voltage reference regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return PTR_ERR(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		/* use external reference voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		ret = regulator_enable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				"enable reference regulator failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		st->vref_mv = regulator_get_voltage(st->vref_reg) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		ret = ltc2632_spi_write(spi, LTC2632_CMD_EXTERNAL_REFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 				0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 				"Set external reference command failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	indio_dev->name = dev_of_node(&spi->dev) ? dev_of_node(&spi->dev)->name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 						 : spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	indio_dev->info = &ltc2632_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	indio_dev->channels = chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	indio_dev->num_channels = chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int ltc2632_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct ltc2632_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (st->vref_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct spi_device_id ltc2632_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	{ "ltc2632-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	{ "ltc2632-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	{ "ltc2632-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	{ "ltc2632-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	{ "ltc2632-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{ "ltc2632-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{ "ltc2634-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{ "ltc2634-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	{ "ltc2634-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	{ "ltc2634-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	{ "ltc2634-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ "ltc2634-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{ "ltc2636-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{ "ltc2636-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	{ "ltc2636-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{ "ltc2636-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	{ "ltc2636-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	{ "ltc2636-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_DEVICE_TABLE(spi, ltc2632_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct of_device_id ltc2632_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		.compatible = "lltc,ltc2632-l12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		.data = &ltc2632_chip_info_tbl[ID_LTC2632L12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		.compatible = "lltc,ltc2632-l10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		.data = &ltc2632_chip_info_tbl[ID_LTC2632L10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.compatible = "lltc,ltc2632-l8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		.data = &ltc2632_chip_info_tbl[ID_LTC2632L8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		.compatible = "lltc,ltc2632-h12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		.data = &ltc2632_chip_info_tbl[ID_LTC2632H12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		.compatible = "lltc,ltc2632-h10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		.data = &ltc2632_chip_info_tbl[ID_LTC2632H10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.compatible = "lltc,ltc2632-h8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		.data = &ltc2632_chip_info_tbl[ID_LTC2632H8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		.compatible = "lltc,ltc2634-l12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		.data = &ltc2632_chip_info_tbl[ID_LTC2634L12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		.compatible = "lltc,ltc2634-l10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		.data = &ltc2632_chip_info_tbl[ID_LTC2634L10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		.compatible = "lltc,ltc2634-l8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		.data = &ltc2632_chip_info_tbl[ID_LTC2634L8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		.compatible = "lltc,ltc2634-h12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.data = &ltc2632_chip_info_tbl[ID_LTC2634H12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.compatible = "lltc,ltc2634-h10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.data = &ltc2632_chip_info_tbl[ID_LTC2634H10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.compatible = "lltc,ltc2634-h8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.data = &ltc2632_chip_info_tbl[ID_LTC2634H8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		.compatible = "lltc,ltc2636-l12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		.data = &ltc2632_chip_info_tbl[ID_LTC2636L12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		.compatible = "lltc,ltc2636-l10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		.data = &ltc2632_chip_info_tbl[ID_LTC2636L10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.compatible = "lltc,ltc2636-l8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.data = &ltc2632_chip_info_tbl[ID_LTC2636L8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		.compatible = "lltc,ltc2636-h12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		.data = &ltc2632_chip_info_tbl[ID_LTC2636H12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.compatible = "lltc,ltc2636-h10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		.data = &ltc2632_chip_info_tbl[ID_LTC2636H10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		.compatible = "lltc,ltc2636-h8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.data = &ltc2632_chip_info_tbl[ID_LTC2636H8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_DEVICE_TABLE(of, ltc2632_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct spi_driver ltc2632_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		.name	= "ltc2632",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		.of_match_table = of_match_ptr(ltc2632_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.probe		= ltc2632_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.remove		= ltc2632_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	.id_table	= ltc2632_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) module_spi_driver(ltc2632_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DESCRIPTION("LTC2632 DAC SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_LICENSE("GPL v2");