Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * IIO DAC driver for NXP LPC18xx DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * UNSUPPORTED hardware features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  - Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  - DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* LPC18XX DAC registers and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LPC18XX_DAC_CR			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  LPC18XX_DAC_CR_VALUE_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  LPC18XX_DAC_CR_VALUE_MASK	0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define  LPC18XX_DAC_CR_BIAS		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPC18XX_DAC_CTRL		0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define  LPC18XX_DAC_CTRL_DMA_ENA	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct lpc18xx_dac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static const struct iio_chan_spec lpc18xx_dac_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.output = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				      BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int lpc18xx_dac_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 				int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct lpc18xx_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		reg = readl(dac->base + LPC18XX_DAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		*val = reg >> LPC18XX_DAC_CR_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		*val &= LPC18XX_DAC_CR_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		*val = regulator_get_voltage(dac->vref) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		*val2 = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int lpc18xx_dac_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				 struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				 int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct lpc18xx_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (val < 0 || val > LPC18XX_DAC_CR_VALUE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		reg = LPC18XX_DAC_CR_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		reg |= val << LPC18XX_DAC_CR_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		mutex_lock(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		writel(reg, dac->base + LPC18XX_DAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		writel(LPC18XX_DAC_CTRL_DMA_ENA, dac->base + LPC18XX_DAC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		mutex_unlock(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct iio_info lpc18xx_dac_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.read_raw = lpc18xx_dac_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.write_raw = lpc18xx_dac_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int lpc18xx_dac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct lpc18xx_dac *dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mutex_init(&dac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	dac->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (IS_ERR(dac->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return PTR_ERR(dac->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	dac->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (IS_ERR(dac->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		dev_err(&pdev->dev, "error getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return PTR_ERR(dac->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	dac->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (IS_ERR(dac->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		dev_err(&pdev->dev, "error getting regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return PTR_ERR(dac->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	indio_dev->info = &lpc18xx_dac_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	indio_dev->channels = lpc18xx_dac_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	indio_dev->num_channels = ARRAY_SIZE(lpc18xx_dac_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret = regulator_enable(dac->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		dev_err(&pdev->dev, "unable to enable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ret = clk_prepare_enable(dac->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		dev_err(&pdev->dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		goto dis_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	writel(0, dac->base + LPC18XX_DAC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	writel(0, dac->base + LPC18XX_DAC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_err(&pdev->dev, "unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dis_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	clk_disable_unprepare(dac->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dis_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	regulator_disable(dac->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int lpc18xx_dac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct lpc18xx_dac *dac = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	writel(0, dac->base + LPC18XX_DAC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	clk_disable_unprepare(dac->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	regulator_disable(dac->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct of_device_id lpc18xx_dac_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{ .compatible = "nxp,lpc1850-dac" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_DEVICE_TABLE(of, lpc18xx_dac_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct platform_driver lpc18xx_dac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.probe	= lpc18xx_dac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.remove	= lpc18xx_dac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.name = "lpc18xx-dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.of_match_table = lpc18xx_dac_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) module_platform_driver(lpc18xx_dac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_DESCRIPTION("LPC18xx DAC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_LICENSE("GPL v2");