Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Maxim Integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * 7-bit, Multi-Channel Sink/Source Current DAC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Maxim Integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DS4422_MAX_DAC_CHANNELS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DS4424_MAX_DAC_CHANNELS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DS4424_DAC_ADDR(chan)   ((chan) + 0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DS4424_SOURCE_I		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DS4424_SINK_I		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DS4424_CHANNEL(chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.type = IIO_CURRENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.channel = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * DS4424 DAC control register 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * [7]		0: to sink; 1: to source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * [6:0]	steps to sink/source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * bit[7] looks like a sign bit, but the value of the register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * not a two's complement code considering the bit[6:0] is a absolute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * distance from the zero point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) union ds4424_raw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		u8 dx:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		u8 source_bit:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) enum ds4424_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	ID_DS4422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	ID_DS4424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct ds4424_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	uint8_t save[DS4424_MAX_DAC_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct regulator *vcc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	uint8_t raw[DS4424_MAX_DAC_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct iio_chan_spec ds4424_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DS4424_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	DS4424_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DS4424_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	DS4424_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int ds4424_get_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			     int *val, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct ds4424_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ret = i2c_smbus_read_byte_data(data->client, DS4424_DAC_ADDR(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	*val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int ds4424_set_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			     int val, struct iio_chan_spec const *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct ds4424_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			DS4424_DAC_ADDR(chan->channel), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	data->raw[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int ds4424_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			   int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	union ds4424_raw_data raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		ret = ds4424_get_value(indio_dev, val, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			pr_err("%s : ds4424_get_value returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 							__func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		raw.bits = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		*val = raw.dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		if (raw.source_bit == DS4424_SINK_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			*val = -*val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int ds4424_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			     int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	union ds4424_raw_data raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (val2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (val < S8_MIN || val > S8_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (val > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			raw.source_bit = DS4424_SOURCE_I;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			raw.dx = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			raw.source_bit = DS4424_SINK_I;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			raw.dx = -val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return ds4424_set_value(indio_dev, raw.bits, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int ds4424_verify_chip(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret = ds4424_get_value(indio_dev, &val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				"%s failed. ret: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int __maybe_unused ds4424_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct ds4424_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	for (i = 0; i < indio_dev->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		data->save[i] = data->raw[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		ret = ds4424_set_value(indio_dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				&indio_dev->channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int __maybe_unused ds4424_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct ds4424_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	for (i = 0; i < indio_dev->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ret = ds4424_set_value(indio_dev, data->save[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				&indio_dev->channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct iio_info ds4424_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.read_raw = ds4424_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.write_raw = ds4424_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int ds4424_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct ds4424_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(&client->dev, "iio dev alloc failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	data->vcc_reg = devm_regulator_get(&client->dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (IS_ERR(data->vcc_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			"Failed to get vcc-supply regulator. err: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				PTR_ERR(data->vcc_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return PTR_ERR(data->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ret = regulator_enable(data->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				"Unable to enable the regulator.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	usleep_range(1000, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = ds4424_verify_chip(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	switch (id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case ID_DS4422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		indio_dev->num_channels = DS4422_MAX_DAC_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case ID_DS4424:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		indio_dev->num_channels = DS4424_MAX_DAC_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				"ds4424: Invalid chip id.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	indio_dev->channels = ds4424_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	indio_dev->info = &ds4424_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				"iio_device_register failed. ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	regulator_disable(data->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int ds4424_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	struct ds4424_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	regulator_disable(data->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct i2c_device_id ds4424_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ "ds4422", ID_DS4422 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ "ds4424", ID_DS4424 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DEVICE_TABLE(i2c, ds4424_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct of_device_id ds4424_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ .compatible = "maxim,ds4422" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ .compatible = "maxim,ds4424" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_DEVICE_TABLE(of, ds4424_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct i2c_driver ds4424_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.name	= "ds4424",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.of_match_table = ds4424_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.pm     = &ds4424_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.probe		= ds4424_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.remove		= ds4424_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.id_table	= ds4424_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) module_i2c_driver(ds4424_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MODULE_DESCRIPTION("Maxim DS4424 DAC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MODULE_AUTHOR("Ismail H. Kose <ismail.kose@maximintegrated.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_AUTHOR("Vishal Sood <vishal.sood@maximintegrated.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_AUTHOR("David Jung <david.jung@maximintegrated.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_LICENSE("GPL v2");