^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IIO DAC driver for Analog Devices AD8801 DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Gwenhael Goavec-Merou
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AD8801_CFG_ADDR_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum ad8801_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ID_AD8801,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ID_AD8803,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct ad8801_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned char dac_cache[8]; /* Value write on each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int vrefh_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int vrefl_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct regulator *vrefh_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct regulator *vrefl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __be16 data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int ad8801_spi_write(struct ad8801_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 channel, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) state->data = cpu_to_be16((channel << AD8801_CFG_ADDR_OFFSET) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return spi_write(state->spi, &state->data, sizeof(state->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int ad8801_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct ad8801_state *state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (val >= 256 || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = ad8801_spi_write(state, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) state->dac_cache[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ad8801_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct iio_chan_spec const *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct ad8801_state *state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *val = state->dac_cache[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *val = state->vrefh_mv - state->vrefl_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *val2 = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *val = state->vrefl_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct iio_info ad8801_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .read_raw = ad8801_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .write_raw = ad8801_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AD8801_CHANNEL(chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .channel = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct iio_chan_spec ad8801_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) AD8801_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AD8801_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AD8801_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AD8801_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AD8801_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AD8801_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AD8801_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AD8801_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int ad8801_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ad8801_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct spi_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) state->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) state->vrefh_reg = devm_regulator_get(&spi->dev, "vrefh");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (IS_ERR(state->vrefh_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(&spi->dev, "Vrefh regulator not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return PTR_ERR(state->vrefh_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = regulator_enable(state->vrefh_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(&spi->dev, "Failed to enable vrefh regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = regulator_get_voltage(state->vrefh_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(&spi->dev, "Failed to read vrefh regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto error_disable_vrefh_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) state->vrefh_mv = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (id->driver_data == ID_AD8803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) state->vrefl_reg = devm_regulator_get(&spi->dev, "vrefl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(state->vrefl_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(&spi->dev, "Vrefl regulator not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = PTR_ERR(state->vrefl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto error_disable_vrefh_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = regulator_enable(state->vrefl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(&spi->dev, "Failed to enable vrefl regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto error_disable_vrefh_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = regulator_get_voltage(state->vrefl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(&spi->dev, "Failed to read vrefl regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto error_disable_vrefl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) state->vrefl_mv = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) state->vrefl_mv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) state->vrefl_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) indio_dev->info = &ad8801_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) indio_dev->channels = ad8801_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) indio_dev->num_channels = ARRAY_SIZE(ad8801_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(&spi->dev, "Failed to register iio device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto error_disable_vrefl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) error_disable_vrefl_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (state->vrefl_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regulator_disable(state->vrefl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) error_disable_vrefh_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regulator_disable(state->vrefh_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int ad8801_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ad8801_state *state = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (state->vrefl_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) regulator_disable(state->vrefl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regulator_disable(state->vrefh_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct spi_device_id ad8801_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {"ad8801", ID_AD8801},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {"ad8803", ID_AD8803},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_DEVICE_TABLE(spi, ad8801_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct spi_driver ad8801_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = "ad8801",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .probe = ad8801_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .remove = ad8801_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .id_table = ad8801_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) module_spi_driver(ad8801_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_AUTHOR("Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_DESCRIPTION("Analog Devices AD8801/AD8803 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags