^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7303 Digital to analog converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/ad7303.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AD7303_CFG_EXTERNAL_VREF BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AD7303_CFG_POWER_DOWN(ch) BIT(11 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD7303_CFG_ADDR_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD7303_CMD_UPDATE_DAC (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * struct ad7303_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @spi: the device for this driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @config: cached config register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @dac_cache: current DAC raw value (chip does not support readback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @vdd_reg: reference to VDD regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @vref_reg: reference to VREF regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @lock: protect writes and cache updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @data: spi transfer buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ad7303_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uint16_t config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) uint8_t dac_cache[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct regulator *vdd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regulator *vref_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __be16 data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int ad7303_write(struct ad7303_state *st, unsigned int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint8_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) st->data = cpu_to_be16(AD7303_CMD_UPDATE_DAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (chan << AD7303_CFG_ADDR_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) st->config | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return spi_write(st->spi, &st->data, sizeof(st->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static ssize_t ad7303_read_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) uintptr_t private, const struct iio_chan_spec *chan, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ad7303_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return sprintf(buf, "%d\n", (bool)(st->config &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) AD7303_CFG_POWER_DOWN(chan->channel)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static ssize_t ad7303_write_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ad7303_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = strtobool(buf, &pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (pwr_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) st->config |= AD7303_CFG_POWER_DOWN(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) st->config &= ~AD7303_CFG_POWER_DOWN(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* There is no noop cmd which allows us to only update the powerdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * mode, so just write one of the DAC channels again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ad7303_write(st, chan->channel, st->dac_cache[chan->channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int ad7303_get_vref(struct ad7303_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct iio_chan_spec const *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (st->config & AD7303_CFG_EXTERNAL_VREF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return regulator_get_voltage(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = regulator_get_voltage(st->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int ad7303_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct iio_chan_spec const *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ad7303_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *val = st->dac_cache[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vref_uv = ad7303_get_vref(st, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (vref_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *val = 2 * vref_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ad7303_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ad7303_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (val >= (1 << chan->scan_type.realbits) || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = ad7303_write(st, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) st->dac_cache[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct iio_info ad7303_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .read_raw = ad7303_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .write_raw = ad7303_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct iio_chan_spec_ext_info ad7303_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .read = ad7303_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .write = ad7303_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AD7303_CHANNEL(chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .channel = (chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .address = (chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .realbits = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .storagebits = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .shift = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ext_info = ad7303_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct iio_chan_spec ad7303_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) AD7303_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) AD7303_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int ad7303_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct ad7303_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) st->vdd_reg = devm_regulator_get(&spi->dev, "Vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (IS_ERR(st->vdd_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return PTR_ERR(st->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = regulator_enable(st->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) st->vref_reg = devm_regulator_get_optional(&spi->dev, "REF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_ERR(st->vref_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = PTR_ERR(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_disable_vdd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) st->vref_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (st->vref_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = regulator_enable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto err_disable_vdd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) st->config |= AD7303_CFG_EXTERNAL_VREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) indio_dev->info = &ad7303_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) indio_dev->channels = ad7303_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) indio_dev->num_channels = ARRAY_SIZE(ad7303_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto err_disable_vref_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) err_disable_vref_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (st->vref_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) err_disable_vdd_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) regulator_disable(st->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int ad7303_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct ad7303_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (st->vref_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) regulator_disable(st->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct of_device_id ad7303_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .compatible = "adi,ad7303", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DEVICE_TABLE(of, ad7303_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct spi_device_id ad7303_spi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { "ad7303", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DEVICE_TABLE(spi, ad7303_spi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct spi_driver ad7303_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "ad7303",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .of_match_table = ad7303_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .probe = ad7303_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .remove = ad7303_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .id_table = ad7303_spi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_spi_driver(ad7303_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_DESCRIPTION("Analog Devices AD7303 DAC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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