Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD5760, AD5780, AD5781, AD5790, AD5791 Voltage Output Digital to Analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/dac/ad5791.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AD5791_DAC_MASK			GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD5791_CMD_READ			BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD5791_CMD_WRITE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD5791_ADDR(addr)		((addr) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD5791_ADDR_NOOP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD5791_ADDR_DAC0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD5791_ADDR_CTRL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD5791_ADDR_CLRCODE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AD5791_ADDR_SW_CTRL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AD5791_CTRL_RBUF		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AD5791_CTRL_OPGND		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AD5791_CTRL_DACTRI		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AD5791_CTRL_BIN2SC		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AD5791_CTRL_SDODIS		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AD5761_CTRL_LINCOMP(x)		((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AD5791_LINCOMP_0_10		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AD5791_LINCOMP_10_12		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AD5791_LINCOMP_12_16		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AD5791_LINCOMP_16_19		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AD5791_LINCOMP_19_20		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AD5780_LINCOMP_0_10		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AD5780_LINCOMP_10_20		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Software Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AD5791_SWCTRL_LDAC		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AD5791_SWCTRL_CLR		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AD5791_SWCTRL_RESET		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AD5791_DAC_PWRDN_6K		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AD5791_DAC_PWRDN_3STATE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * struct ad5791_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * @get_lin_comp:	function pointer to the device specific function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct ad5791_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int (*get_lin_comp)	(unsigned int span);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * struct ad5791_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * @spi:			spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * @reg_vdd:		positive supply regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @reg_vss:		negative supply regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @chip_info:		chip model specific constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * @vref_mv:		actual reference voltage used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * @vref_neg_mv:	voltage of the negative supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * @ctrl:		control regster cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @pwr_down_mode:	current power down mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @pwr_down:		true if device is powered down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @data:		spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct ad5791_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct regulator		*reg_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct regulator		*reg_vss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	const struct ad5791_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned short			vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned int			vref_neg_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned			ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned			pwr_down_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	bool				pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		__be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	} data[3] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum ad5791_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ID_AD5760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ID_AD5780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ID_AD5781,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ID_AD5791,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			      AD5791_ADDR(addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			      (val & AD5791_DAC_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return spi_write(st->spi, &st->data[0].d8[1], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct spi_transfer xfers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			.tx_buf = &st->data[0].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			.bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			.len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			.cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			.tx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			.rx_buf = &st->data[2].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			.bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			.len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	st->data[0].d32 = cpu_to_be32(AD5791_CMD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			      AD5791_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	st->data[1].d32 = cpu_to_be32(AD5791_ADDR(AD5791_ADDR_NOOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	*val = be32_to_cpu(st->data[2].d32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char * const ad5791_powerdown_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	"6kohm_to_gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	"three_state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int ad5791_get_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return st->pwr_down_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int ad5791_set_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	const struct iio_chan_spec *chan, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	st->pwr_down_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct iio_enum ad5791_powerdown_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.items = ad5791_powerdown_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.num_items = ARRAY_SIZE(ad5791_powerdown_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.get = ad5791_get_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.set = ad5791_set_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static ssize_t ad5791_read_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	uintptr_t private, const struct iio_chan_spec *chan, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return sprintf(buf, "%d\n", st->pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static ssize_t ad5791_write_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	bool pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ret = strtobool(buf, &pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!pwr_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		st->ctrl &= ~(AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (st->pwr_down_mode == AD5791_DAC_PWRDN_6K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			st->ctrl |= AD5791_CTRL_OPGND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		else if (st->pwr_down_mode == AD5791_DAC_PWRDN_3STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			st->ctrl |= AD5791_CTRL_DACTRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	st->pwr_down = pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int ad5791_get_lin_comp(unsigned int span)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (span <= 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return AD5791_LINCOMP_0_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	else if (span <= 12000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return AD5791_LINCOMP_10_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	else if (span <= 16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return AD5791_LINCOMP_12_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	else if (span <= 19000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return AD5791_LINCOMP_16_19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return AD5791_LINCOMP_19_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int ad5780_get_lin_comp(unsigned int span)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (span <= 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return AD5780_LINCOMP_0_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return AD5780_LINCOMP_10_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct ad5791_chip_info ad5791_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	[ID_AD5760] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.get_lin_comp = ad5780_get_lin_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	[ID_AD5780] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.get_lin_comp = ad5780_get_lin_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	[ID_AD5781] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.get_lin_comp = ad5791_get_lin_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	[ID_AD5791] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.get_lin_comp = ad5791_get_lin_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int ad5791_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			   int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			   int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			   long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	u64 val64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		ret = ad5791_spi_read(st, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		*val &= AD5791_DAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		*val >>= chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		*val = st->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		*val2 = (1 << chan->scan_type.realbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		val64 = (((u64)st->vref_neg_mv) << chan->scan_type.realbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		do_div(val64, st->vref_mv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		*val = -val64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct iio_chan_spec_ext_info ad5791_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.shared = IIO_SHARED_BY_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.read = ad5791_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.write = ad5791_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		 &ad5791_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5791_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AD5791_CHAN(bits, _shift) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.output = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.address = AD5791_ADDR_DAC0,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.channel = 0,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		BIT(IIO_CHAN_INFO_OFFSET),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.scan_type = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.sign = 'u',				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.realbits = (bits),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.storagebits = 24,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.shift = (_shift),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	},						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.ext_info = ad5791_ext_info,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct iio_chan_spec ad5791_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	[ID_AD5760] = AD5791_CHAN(16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	[ID_AD5780] = AD5791_CHAN(18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	[ID_AD5781] = AD5791_CHAN(18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	[ID_AD5791] = AD5791_CHAN(20, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int ad5791_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			    int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			    int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			    long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		val &= GENMASK(chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		val <<= chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return ad5791_spi_write(st, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct iio_info ad5791_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.read_raw = &ad5791_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.write_raw = &ad5791_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int ad5791_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct ad5791_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct ad5791_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	int ret, pos_voltage_uv = 0, neg_voltage_uv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	st->reg_vdd = devm_regulator_get(&spi->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (!IS_ERR(st->reg_vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		ret = regulator_enable(st->reg_vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		ret = regulator_get_voltage(st->reg_vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			goto error_disable_reg_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		pos_voltage_uv = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	st->reg_vss = devm_regulator_get(&spi->dev, "vss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (!IS_ERR(st->reg_vss)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = regulator_enable(st->reg_vss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			goto error_disable_reg_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		ret = regulator_get_voltage(st->reg_vss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			goto error_disable_reg_neg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		neg_voltage_uv = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	st->pwr_down = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (!IS_ERR(st->reg_vss) && !IS_ERR(st->reg_vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		st->vref_mv = (pos_voltage_uv + neg_voltage_uv) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		st->vref_neg_mv = neg_voltage_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	} else if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		st->vref_mv = pdata->vref_pos_mv + pdata->vref_neg_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		st->vref_neg_mv = pdata->vref_neg_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		dev_warn(&spi->dev, "reference voltage unspecified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ret = ad5791_spi_write(st, AD5791_ADDR_SW_CTRL, AD5791_SWCTRL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		goto error_disable_reg_neg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	st->chip_info =	&ad5791_chip_info_tbl[spi_get_device_id(spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 					      ->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	st->ctrl = AD5761_CTRL_LINCOMP(st->chip_info->get_lin_comp(st->vref_mv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		  | ((pdata && pdata->use_rbuf_gain2) ? 0 : AD5791_CTRL_RBUF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		  AD5791_CTRL_BIN2SC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		goto error_disable_reg_neg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	indio_dev->info = &ad5791_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	indio_dev->channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		= &ad5791_channels[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	indio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	indio_dev->name = spi_get_device_id(st->spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		goto error_disable_reg_neg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) error_disable_reg_neg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	if (!IS_ERR(st->reg_vss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		regulator_disable(st->reg_vss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) error_disable_reg_pos:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (!IS_ERR(st->reg_vdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		regulator_disable(st->reg_vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int ad5791_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	struct ad5791_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (!IS_ERR(st->reg_vdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		regulator_disable(st->reg_vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (!IS_ERR(st->reg_vss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		regulator_disable(st->reg_vss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const struct spi_device_id ad5791_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{"ad5760", ID_AD5760},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	{"ad5780", ID_AD5780},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{"ad5781", ID_AD5781},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{"ad5790", ID_AD5791},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	{"ad5791", ID_AD5791},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_DEVICE_TABLE(spi, ad5791_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct spi_driver ad5791_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		   .name = "ad5791",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.probe = ad5791_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	.remove = ad5791_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.id_table = ad5791_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) module_spi_driver(ad5791_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_DESCRIPTION("Analog Devices AD5760/AD5780/AD5781/AD5790/AD5791 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_LICENSE("GPL v2");