^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD5770R Digital to analog converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADI_SPI_IF_CONFIG_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADI_SPI_IF_CONFIG_B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADI_SPI_IF_DEVICE_CONFIG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADI_SPI_IF_CHIP_TYPE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADI_SPI_IF_PRODUCT_ID_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADI_SPI_IF_PRODUCT_ID_H 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADI_SPI_IF_CHIP_GRADE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADI_SPI_IF_SCRACTH_PAD 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADI_SPI_IF_SPI_REVISION 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADI_SPI_IF_SPI_VENDOR_L 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADI_SPI_IF_SPI_VENDOR_H 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADI_SPI_IF_SPI_STREAM_MODE 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADI_SPI_IF_CONFIG_C 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADI_SPI_IF_STATUS_A 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ADI_SPI_IF_CONFIG_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADI_SPI_IF_SW_RESET_MSK (BIT(0) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADI_SPI_IF_SW_RESET_SEL(x) ((x) & ADI_SPI_IF_SW_RESET_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADI_SPI_IF_ADDR_ASC_MSK (BIT(2) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADI_SPI_IF_ADDR_ASC_SEL(x) (((x) << 2) & ADI_SPI_IF_ADDR_ASC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* ADI_SPI_IF_CONFIG_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADI_SPI_IF_SINGLE_INS_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADI_SPI_IF_SINGLE_INS_SEL(x) FIELD_PREP(ADI_SPI_IF_SINGLE_INS_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADI_SPI_IF_SHORT_INS_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADI_SPI_IF_SHORT_INS_SEL(x) FIELD_PREP(ADI_SPI_IF_SINGLE_INS_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ADI_SPI_IF_CONFIG_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADI_SPI_IF_STRICT_REG_MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADI_SPI_IF_STRICT_REG_GET(x) FIELD_GET(ADI_SPI_IF_STRICT_REG_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* AD5770R configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD5770R_CHANNEL_CONFIG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD5770R_OUTPUT_RANGE(ch) (0x15 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD5770R_FILTER_RESISTOR(ch) (0x1D + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AD5770R_REFERENCE 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AD5770R_DAC_LSB(ch) (0x26 + 2 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD5770R_DAC_MSB(ch) (0x27 + 2 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AD5770R_CH_SELECT 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD5770R_CH_ENABLE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* AD5770R_CHANNEL_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AD5770R_CFG_CH0_SINK_EN(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AD5770R_CFG_SHUTDOWN_B(x, ch) (((x) & 0x1) << (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* AD5770R_OUTPUT_RANGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD5770R_RANGE_OUTPUT_SCALING(x) (((x) & GENMASK(5, 0)) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AD5770R_RANGE_MODE(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* AD5770R_REFERENCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD5770R_REF_RESISTOR_SEL(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD5770R_REF_SEL(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* AD5770R_CH_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AD5770R_CH_SET(x, ch) (((x) & 0x1) << (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AD5770R_MAX_CHANNELS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AD5770R_MAX_CH_MODES 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AD5770R_LOW_VREF_mV 1250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AD5770R_HIGH_VREF_mV 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum ad5770r_ch0_modes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) AD5770R_CH0_0_300 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AD5770R_CH0_NEG_60_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AD5770R_CH0_NEG_60_300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum ad5770r_ch1_modes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) AD5770R_CH1_0_140_LOW_HEAD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) AD5770R_CH1_0_140_LOW_NOISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AD5770R_CH1_0_250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum ad5770r_ch2_5_modes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) AD5770R_CH_LOW_RANGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AD5770R_CH_HIGH_RANGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum ad5770r_ref_v {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) AD5770R_EXT_2_5_V = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AD5770R_INT_1_25_V_OUT_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AD5770R_EXT_1_25_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AD5770R_INT_1_25_V_OUT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum ad5770r_output_filter_resistor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AD5770R_FILTER_60_OHM = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AD5770R_FILTER_5_6_KOHM = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) AD5770R_FILTER_11_2_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AD5770R_FILTER_22_2_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AD5770R_FILTER_44_4_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) AD5770R_FILTER_104_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct ad5770r_out_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 out_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 out_range_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * struct ad5770R_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @spi: spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @regmap: regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @vref_reg: fixed regulator for reference configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @gpio_reset: gpio descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @output_mode: array contains channels output ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @vref: reference value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @ch_pwr_down: powerdown flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @internal_ref: internal reference flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @external_res: external 2.5k resistor flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @transf_buf: cache aligned buffer for spi read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ad5770r_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct regulator *vref_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ad5770r_out_range output_mode[AD5770R_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool ch_pwr_down[AD5770R_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool internal_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool external_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 transf_buf[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct regmap_config ad5770r_spi_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .read_flag_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct ad5770r_output_modes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct ad5770r_output_modes ad5770r_rng_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0, AD5770R_CH0_0_300, 0, 300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0, AD5770R_CH0_NEG_60_0, -60, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0, AD5770R_CH0_NEG_60_300, -60, 300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 1, AD5770R_CH1_0_140_LOW_HEAD, 0, 140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 1, AD5770R_CH1_0_140_LOW_NOISE, 0, 140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 1, AD5770R_CH1_0_250, 0, 250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 2, AD5770R_CH_LOW_RANGE, 0, 55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 2, AD5770R_CH_HIGH_RANGE, 0, 150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 3, AD5770R_CH_LOW_RANGE, 0, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 3, AD5770R_CH_HIGH_RANGE, 0, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 4, AD5770R_CH_LOW_RANGE, 0, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 4, AD5770R_CH_HIGH_RANGE, 0, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 5, AD5770R_CH_LOW_RANGE, 0, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 5, AD5770R_CH_HIGH_RANGE, 0, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned int ad5770r_filter_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 153, 357, 715, 1400, 2800, 262000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned int ad5770r_filter_reg_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AD5770R_FILTER_104_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) AD5770R_FILTER_44_4_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) AD5770R_FILTER_22_2_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) AD5770R_FILTER_11_2_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) AD5770R_FILTER_5_6_KOHM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) AD5770R_FILTER_60_OHM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int ad5770r_set_output_mode(struct ad5770r_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const struct ad5770r_out_range *out_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) regval = AD5770R_RANGE_OUTPUT_SCALING(out_mode->out_scale) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) AD5770R_RANGE_MODE(out_mode->out_range_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return regmap_write(st->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) AD5770R_OUTPUT_RANGE(channel), regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int ad5770r_set_reference(struct ad5770r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) regval = AD5770R_REF_RESISTOR_SEL(st->external_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (st->internal_ref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regval |= AD5770R_REF_SEL(AD5770R_INT_1_25_V_OUT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) switch (st->vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case AD5770R_LOW_VREF_mV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regval |= AD5770R_REF_SEL(AD5770R_EXT_1_25_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case AD5770R_HIGH_VREF_mV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regval |= AD5770R_REF_SEL(AD5770R_EXT_2_5_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) regval = AD5770R_REF_SEL(AD5770R_INT_1_25_V_OUT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return regmap_write(st->regmap, AD5770R_REFERENCE, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ad5770r_soft_reset(struct ad5770r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return regmap_write(st->regmap, ADI_SPI_IF_CONFIG_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ADI_SPI_IF_SW_RESET_SEL(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ad5770r_reset(struct ad5770r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Perform software reset if no GPIO provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!st->gpio_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ad5770r_soft_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) gpiod_set_value_cansleep(st->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) gpiod_set_value_cansleep(st->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* data must not be written during reset timeframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int ad5770r_get_range(struct ad5770r_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ch, int *min, int *max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 tbl_ch, tbl_mode, out_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) out_range = st->output_mode[ch].out_range_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < AD5770R_MAX_CH_MODES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tbl_ch = ad5770r_rng_tbl[i].ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tbl_mode = ad5770r_rng_tbl[i].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (tbl_ch == ch && tbl_mode == out_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *min = ad5770r_rng_tbl[i].min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *max = ad5770r_rng_tbl[i].max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int ad5770r_get_filter_freq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const struct iio_chan_spec *chan, int *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int regval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = regmap_read(st->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) AD5770R_FILTER_RESISTOR(chan->channel), ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < ARRAY_SIZE(ad5770r_filter_reg_vals); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (regval == ad5770r_filter_reg_vals[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (i == ARRAY_SIZE(ad5770r_filter_reg_vals))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *freq = ad5770r_filter_freqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int ad5770r_set_filter_freq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int regval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) for (i = 0; i < ARRAY_SIZE(ad5770r_filter_freqs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ad5770r_filter_freqs[i] >= freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (i == ARRAY_SIZE(ad5770r_filter_freqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regval = ad5770r_filter_reg_vals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return regmap_write(st->regmap, AD5770R_FILTER_RESISTOR(chan->channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int ad5770r_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int max, min, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u16 buf16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = regmap_bulk_read(st->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chan->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) st->transf_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) buf16 = st->transf_buf[0] + (st->transf_buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *val = buf16 >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = ad5770r_get_range(st, chan->channel, &min, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *val = max - min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* There is no sign bit. (negative current is mapped from 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * (sourced/sinked) current = raw * scale + offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * where offset in case of CH0 can be negative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *val2 = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ad5770r_get_filter_freq(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = ad5770r_get_range(st, chan->channel, &min, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *val = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int ad5770r_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) st->transf_buf[0] = ((u16)val >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) st->transf_buf[1] = (val & GENMASK(5, 0)) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return regmap_bulk_write(st->regmap, chan->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) st->transf_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ad5770r_set_filter_freq(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int ad5770r_read_freq_avail(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) const int **vals, int *type, int *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *type = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *vals = ad5770r_filter_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *length = ARRAY_SIZE(ad5770r_filter_freqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int ad5770r_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return regmap_read(st->regmap, reg, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return regmap_write(st->regmap, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct iio_info ad5770r_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .read_raw = ad5770r_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .write_raw = ad5770r_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .read_avail = ad5770r_read_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .debugfs_reg_access = &ad5770r_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int ad5770r_store_output_range(struct ad5770r_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int min, int max, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (i = 0; i < AD5770R_MAX_CH_MODES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ad5770r_rng_tbl[i].ch != index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ad5770r_rng_tbl[i].min != min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ad5770r_rng_tbl[i].max != max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) st->output_mode[index].out_range_mode = ad5770r_rng_tbl[i].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static ssize_t ad5770r_read_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return sprintf(buf, "%d\n", st->ch_pwr_down[chan->channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static ssize_t ad5770r_write_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct ad5770r_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) bool readin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = kstrtobool(buf, &readin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) readin = !readin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) regval = AD5770R_CFG_SHUTDOWN_B(readin, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (chan->channel == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) st->output_mode[0].out_range_mode > AD5770R_CH0_0_300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regval |= AD5770R_CFG_CH0_SINK_EN(readin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mask = BIT(chan->channel) + BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mask = BIT(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_update_bits(st->regmap, AD5770R_CHANNEL_CONFIG, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) regval = AD5770R_CH_SET(readin, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = regmap_update_bits(st->regmap, AD5770R_CH_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) BIT(chan->channel), regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) st->ch_pwr_down[chan->channel] = !readin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct iio_chan_spec_ext_info ad5770r_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .read = ad5770r_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .write = ad5770r_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define AD5770R_IDAC_CHANNEL(index, reg) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .type = IIO_CURRENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .address = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .channel = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) BIT(IIO_CHAN_INFO_OFFSET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .info_mask_shared_by_type_available = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .ext_info = ad5770r_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct iio_chan_spec ad5770r_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) AD5770R_IDAC_CHANNEL(0, AD5770R_DAC_MSB(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) AD5770R_IDAC_CHANNEL(1, AD5770R_DAC_MSB(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) AD5770R_IDAC_CHANNEL(2, AD5770R_DAC_MSB(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) AD5770R_IDAC_CHANNEL(3, AD5770R_DAC_MSB(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) AD5770R_IDAC_CHANNEL(4, AD5770R_DAC_MSB(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) AD5770R_IDAC_CHANNEL(5, AD5770R_DAC_MSB(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int ad5770r_channel_config(struct ad5770r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret, tmp[2], min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct fwnode_handle *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) num = device_get_child_node_count(&st->spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (num != AD5770R_MAX_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) device_for_each_child_node(&st->spi->dev, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = fwnode_property_read_u32(child, "reg", &num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto err_child_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (num >= AD5770R_MAX_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto err_child_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = fwnode_property_read_u32_array(child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "adi,range-microamp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) tmp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto err_child_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) min = tmp[0] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) max = tmp[1] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = ad5770r_store_output_range(st, min, max, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto err_child_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) err_child_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) fwnode_handle_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int ad5770r_init(struct ad5770r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (IS_ERR(st->gpio_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return PTR_ERR(st->gpio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Perform a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = ad5770r_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Set output range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = ad5770r_channel_config(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i = 0; i < AD5770R_MAX_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = ad5770r_set_output_mode(st, &st->output_mode[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) st->external_res = fwnode_property_read_bool(st->spi->dev.fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "adi,external-resistor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = ad5770r_set_reference(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Set outputs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = regmap_write(st->regmap, AD5770R_CHANNEL_CONFIG, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = regmap_write(st->regmap, AD5770R_CH_ENABLE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) for (i = 0; i < AD5770R_MAX_CHANNELS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) st->ch_pwr_down[i] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void ad5770r_disable_regulator(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct ad5770r_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int ad5770r_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct ad5770r_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) regmap = devm_regmap_init_spi(spi, &ad5770r_spi_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(&spi->dev, "Error initializing spi regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) st->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!IS_ERR(st->vref_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = regulator_enable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "Failed to enable vref regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = devm_add_action_or_reset(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ad5770r_disable_regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = regulator_get_voltage(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) st->vref = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (PTR_ERR(st->vref_reg) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) st->vref = AD5770R_LOW_VREF_mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) st->internal_ref = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return PTR_ERR(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) indio_dev->info = &ad5770r_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) indio_dev->channels = ad5770r_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) indio_dev->num_channels = ARRAY_SIZE(ad5770r_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = ad5770r_init(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&spi->dev, "AD5770R init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return devm_iio_device_register(&st->spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const struct of_device_id ad5770r_of_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { .compatible = "adi,ad5770r", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MODULE_DEVICE_TABLE(of, ad5770r_of_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const struct spi_device_id ad5770r_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { "ad5770r", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MODULE_DEVICE_TABLE(spi, ad5770r_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct spi_driver ad5770r_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .of_match_table = ad5770r_of_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .probe = ad5770r_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .id_table = ad5770r_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) module_spi_driver(ad5770r_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MODULE_AUTHOR("Mircea Caprioru <mircea.caprioru@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) MODULE_DESCRIPTION("Analog Devices AD5770R IDAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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