Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Digital to Analog Converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AD5764_REG_SF_NOP			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AD5764_REG_SF_CONFIG			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AD5764_REG_SF_CLEAR			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AD5764_REG_SF_LOAD			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AD5764_REG_DATA(x)			((2 << 3) | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD5764_REG_COARSE_GAIN(x)		((3 << 3) | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD5764_REG_FINE_GAIN(x)			((4 << 3) | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD5764_REG_OFFSET(x)			((5 << 3) | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD5764_NUM_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * struct ad5764_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @int_vref:	Value of the internal reference voltage in uV - 0 if external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *		reference voltage is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @channels:	channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct ad5764_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned long int_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * struct ad5764_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @spi:		spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @chip_info:		chip info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * @vref_reg:		vref supply regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * @lock:		lock to protect the data buffer during SPI ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * @data:		spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct ad5764_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	const struct ad5764_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct regulator_bulk_data	vref_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct mutex			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		__be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	} data[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) enum ad5764_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ID_AD5744,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ID_AD5744R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	ID_AD5764,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ID_AD5764R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define AD5764_CHANNEL(_chan, _bits) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.output = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.channel = (_chan),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.address = (_chan),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		BIT(IIO_CHAN_INFO_SCALE) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		BIT(IIO_CHAN_INFO_CALIBSCALE) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		BIT(IIO_CHAN_INFO_CALIBBIAS),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.realbits = (_bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.storagebits = 16,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.shift = 16 - (_bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DECLARE_AD5764_CHANNELS(_name, _bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) const struct iio_chan_spec _name##_channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	AD5764_CHANNEL(0, (_bits)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	AD5764_CHANNEL(1, (_bits)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	AD5764_CHANNEL(2, (_bits)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	AD5764_CHANNEL(3, (_bits)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static DECLARE_AD5764_CHANNELS(ad5764, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static DECLARE_AD5764_CHANNELS(ad5744, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct ad5764_chip_info ad5764_chip_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[ID_AD5744] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.int_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.channels = ad5744_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[ID_AD5744R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.int_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.channels = ad5744_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[ID_AD5764] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.int_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.channels = ad5764_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	[ID_AD5764R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.int_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.channels = ad5764_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct ad5764_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	st->data[0].d32 = cpu_to_be32((reg << 16) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = spi_write(st->spi, &st->data[0].d8[1], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct ad5764_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			.tx_buf = &st->data[0].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			.len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			.cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			.rx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			.len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		*val = be32_to_cpu(st->data[1].d32) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return AD5764_REG_DATA(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return AD5764_REG_OFFSET(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return AD5764_REG_FINE_GAIN(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int ad5764_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct iio_chan_spec const *chan, int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	const int max_val = (1 << chan->scan_type.realbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		val <<= chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		if (val >= 128 || val < -128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (val >= 32 || val < -32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	reg = ad5764_chan_info_to_reg(chan, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return ad5764_write(indio_dev, reg, (u16)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int ad5764_get_channel_vref(struct ad5764_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (st->chip_info->int_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return st->chip_info->int_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int ad5764_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct iio_chan_spec const *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct ad5764_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		reg = AD5764_REG_DATA(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		ret = ad5764_read(indio_dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		*val >>= chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		reg = AD5764_REG_OFFSET(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ret = ad5764_read(indio_dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		*val = sign_extend32(*val, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		reg = AD5764_REG_FINE_GAIN(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		ret = ad5764_read(indio_dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		*val = sign_extend32(*val, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		/* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		vref = ad5764_get_channel_vref(st, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		if (vref < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		*val = vref * 4 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		*val = -(1 << chan->scan_type.realbits) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct iio_info ad5764_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.read_raw = ad5764_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.write_raw = ad5764_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int ad5764_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	enum ad5764_type type = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct ad5764_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (indio_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		dev_err(&spi->dev, "Failed to allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	st->chip_info = &ad5764_chip_infos[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	indio_dev->info = &ad5764_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	indio_dev->num_channels = AD5764_NUM_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (st->chip_info->int_vref == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		st->vref_reg[0].supply = "vrefAB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		st->vref_reg[1].supply = "vrefCD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		ret = devm_regulator_bulk_get(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			ARRAY_SIZE(st->vref_reg), st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			dev_err(&spi->dev, "Failed to request vref regulators: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		ret = regulator_bulk_enable(ARRAY_SIZE(st->vref_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			dev_err(&spi->dev, "Failed to enable vref regulators: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (st->chip_info->int_vref == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int ad5764_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct ad5764_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (st->chip_info->int_vref == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct spi_device_id ad5764_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{ "ad5744", ID_AD5744 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ "ad5744r", ID_AD5744R },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	{ "ad5764", ID_AD5764 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{ "ad5764r", ID_AD5764R },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_DEVICE_TABLE(spi, ad5764_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct spi_driver ad5764_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.name = "ad5764",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.probe = ad5764_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.remove = ad5764_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.id_table = ad5764_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) module_spi_driver(ad5764_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_DESCRIPTION("Analog Devices AD5744/AD5744R/AD5764/AD5764R DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_LICENSE("GPL v2");