^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD5721, AD5721R, AD5761, AD5761R, Voltage Output Digital to Analog Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Qtechnology A/S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2016 Ricardo Ribalda <ribalda@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/ad5761.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AD5761_ADDR(addr) ((addr & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AD5761_ADDR_NOOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AD5761_ADDR_DAC_WRITE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AD5761_ADDR_CTRL_WRITE_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AD5761_ADDR_SW_DATA_RESET 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AD5761_ADDR_DAC_READ 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AD5761_ADDR_CTRL_READ_REG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD5761_ADDR_SW_FULL_RESET 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD5761_CTRL_USE_INTVREF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD5761_CTRL_ETS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * struct ad5761_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @int_vref: Value of the internal reference voltage in mV - 0 if external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * reference voltage is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @channel: channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ad5761_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long int_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct iio_chan_spec channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct ad5761_range_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum ad5761_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ID_AD5721,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ID_AD5721R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ID_AD5761,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ID_AD5761R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * struct ad5761_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @spi: spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @vref_reg: reference voltage regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @use_intref: true when the internal voltage reference is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @vref: actual voltage reference in mVolts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @range: output range mode used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @lock: lock to protect the data buffer during SPI ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @data: cache aligned spi buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ad5761_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct regulator *vref_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool use_intref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum ad5761_voltage_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } data[3] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct ad5761_range_params ad5761_range_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [AD5761_VOLTAGE_RANGE_M10V_10V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .m = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .c = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [AD5761_VOLTAGE_RANGE_0V_10V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .m = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [AD5761_VOLTAGE_RANGE_M5V_5V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .m = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .c = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [AD5761_VOLTAGE_RANGE_0V_5V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .m = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [AD5761_VOLTAGE_RANGE_M2V5_7V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .m = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .c = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [AD5761_VOLTAGE_RANGE_M3V_3V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .m = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .c = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [AD5761_VOLTAGE_RANGE_0V_16V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .m = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [AD5761_VOLTAGE_RANGE_0V_20V] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .m = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int _ad5761_spi_write(struct ad5761_state *st, u8 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return spi_write(st->spi, &st->data[0].d8[1], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int ad5761_spi_write(struct iio_dev *indio_dev, u8 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct ad5761_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = _ad5761_spi_write(st, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int _ad5761_spi_read(struct ad5761_state *st, u8 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct spi_transfer xfers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .tx_buf = &st->data[0].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .cs_change = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .tx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .rx_buf = &st->data[2].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) st->data[1].d32 = cpu_to_be32(AD5761_ADDR(AD5761_ADDR_NOOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *val = be32_to_cpu(st->data[2].d32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int ad5761_spi_read(struct iio_dev *indio_dev, u8 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct ad5761_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = _ad5761_spi_read(st, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int ad5761_spi_set_range(struct ad5761_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum ad5761_voltage_range range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u16 aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) aux = (range & 0x7) | AD5761_CTRL_ETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (st->use_intref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) aux |= AD5761_CTRL_USE_INTVREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = _ad5761_spi_write(st, AD5761_ADDR_SW_FULL_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = _ad5761_spi_write(st, AD5761_ADDR_CTRL_WRITE_REG, aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) st->range = range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int ad5761_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct ad5761_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = ad5761_spi_read(indio_dev, AD5761_ADDR_DAC_READ, &aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *val = aux >> chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *val = st->vref * ad5761_range_params[st->range].m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *val /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *val = -(1 << chan->scan_type.realbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *val *= ad5761_range_params[st->range].c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *val /= ad5761_range_params[st->range].m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ad5761_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u16 aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (mask != IIO_CHAN_INFO_RAW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (val2 || (val << chan->scan_type.shift) > 0xffff || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) aux = val << chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ad5761_spi_write(indio_dev, AD5761_ADDR_DAC_WRITE, aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct iio_info ad5761_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .read_raw = &ad5761_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .write_raw = &ad5761_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AD5761_CHAN(_bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .realbits = (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .shift = 16 - (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct ad5761_chip_info ad5761_chip_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [ID_AD5721] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .int_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .channel = AD5761_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [ID_AD5721R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .int_vref = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .channel = AD5761_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [ID_AD5761] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .int_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .channel = AD5761_CHAN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [ID_AD5761R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .int_vref = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .channel = AD5761_CHAN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int ad5761_get_vref(struct ad5761_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct ad5761_chip_info *chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) st->vref_reg = devm_regulator_get_optional(&st->spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (PTR_ERR(st->vref_reg) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Use Internal regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!chip_info->int_vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "Voltage reference not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) st->use_intref = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) st->vref = chip_info->int_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (IS_ERR(st->vref_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "Error getting voltage reference regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return PTR_ERR(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = regulator_enable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "Failed to enable voltage reference\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = regulator_get_voltage(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "Failed to get voltage reference value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto disable_regulator_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret < 2000000 || ret > 3000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_warn(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "Invalid external voltage ref. value %d uV\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) goto disable_regulator_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) st->vref = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) st->use_intref = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) disable_regulator_vref:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) st->vref_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int ad5761_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct iio_dev *iio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct ad5761_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct ad5761_chip_info *chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &ad5761_chip_infos[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enum ad5761_voltage_range voltage_range = AD5761_VOLTAGE_RANGE_0V_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct ad5761_platform_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) iio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spi_set_drvdata(spi, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = ad5761_get_vref(st, chip_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) voltage_range = pdata->voltage_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = ad5761_spi_set_range(st, voltage_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto disable_regulator_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) iio_dev->info = &ad5761_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) iio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) iio_dev->channels = &chip_info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) iio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) iio_dev->name = spi_get_device_id(st->spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = iio_device_register(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto disable_regulator_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) disable_regulator_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!IS_ERR_OR_NULL(st->vref_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int ad5761_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct iio_dev *iio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct ad5761_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) iio_device_unregister(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!IS_ERR_OR_NULL(st->vref_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regulator_disable(st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct spi_device_id ad5761_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {"ad5721", ID_AD5721},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {"ad5721r", ID_AD5721R},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {"ad5761", ID_AD5761},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {"ad5761r", ID_AD5761R},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DEVICE_TABLE(spi, ad5761_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct spi_driver ad5761_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .name = "ad5761",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .probe = ad5761_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .remove = ad5761_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .id_table = ad5761_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) module_spi_driver(ad5761_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_AUTHOR("Ricardo Ribalda <ribalda@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_DESCRIPTION("Analog Devices AD5721, AD5721R, AD5761, AD5761R driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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