Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_data/ad5755.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AD5755_NUM_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AD5755_ADDR(x)			((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AD5755_WRITE_REG_DATA(chan)	(chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD5755_WRITE_REG_GAIN(chan)	(0x08 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD5755_WRITE_REG_OFFSET(chan)	(0x10 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD5755_WRITE_REG_CTRL(chan)	(0x1c | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD5755_READ_REG_DATA(chan)	(chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD5755_READ_REG_CTRL(chan)	(0x4 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD5755_READ_REG_GAIN(chan)	(0x8 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD5755_READ_REG_OFFSET(chan)	(0xc | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD5755_READ_REG_CLEAR(chan)	(0x10 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AD5755_READ_REG_SLEW(chan)	(0x14 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AD5755_READ_REG_STATUS		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AD5755_READ_REG_MAIN		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AD5755_READ_REG_DC_DC		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AD5755_CTRL_REG_SLEW	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AD5755_CTRL_REG_MAIN	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AD5755_CTRL_REG_DAC	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AD5755_CTRL_REG_DC_DC	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AD5755_CTRL_REG_SW	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AD5755_READ_FLAG 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AD5755_NOOP 0x1CE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AD5755_DAC_INT_EN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AD5755_DAC_CLR_EN			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AD5755_DAC_OUT_EN			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AD5755_DAC_DC_DC_EN			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AD5755_DAC_VOLTAGE_OVERRANGE_EN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AD5755_DC_DC_MAXV			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AD5755_DC_DC_FREQ_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AD5755_DC_DC_PHASE_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AD5755_EXT_DC_DC_COMP_RES		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AD5755_SLEW_STEP_SIZE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AD5755_SLEW_RATE_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AD5755_SLEW_ENABLE			BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * struct ad5755_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * @channel_template:	channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * @calib_shift:	shift for the calibration data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * @has_voltage_out:	whether the chip has voltage outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct ad5755_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	const struct iio_chan_spec channel_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned int calib_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	bool has_voltage_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * struct ad5755_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @spi:	spi device the driver is attached to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @chip_info:	chip model specific constants, available modes etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @pwr_down:	bitmask which contains  hether a channel is powered down or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * @ctrl:	software shadow of the channel ctrl registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * @channels:	iio channel spec for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * @lock:	lock to protect the data buffer during SPI ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * @data:	spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) struct ad5755_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	const struct ad5755_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned int			pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned int			ctrl[AD5755_NUM_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct iio_chan_spec		channels[AD5755_NUM_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct mutex			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		__be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	} data[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum ad5755_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ID_AD5755,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ID_AD5757,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ID_AD5735,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ID_AD5737,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const int ad5755_dcdc_freq_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{ 250000, AD5755_DC_DC_FREQ_250kHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ 410000, AD5755_DC_DC_FREQ_410kHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ 650000, AD5755_DC_DC_FREQ_650kHZ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const int ad5755_dcdc_maxv_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ 23000000, AD5755_DC_DC_MAXV_23V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ 24500000, AD5755_DC_DC_MAXV_24V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ 27000000, AD5755_DC_DC_MAXV_27V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ 29500000, AD5755_DC_DC_MAXV_29V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const int ad5755_slew_rate_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ 64000, AD5755_SLEW_RATE_64k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ 32000, AD5755_SLEW_RATE_32k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ 16000, AD5755_SLEW_RATE_16k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ 8000, AD5755_SLEW_RATE_8k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ 4000, AD5755_SLEW_RATE_4k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ 2000, AD5755_SLEW_RATE_2k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ 1000, AD5755_SLEW_RATE_1k },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ 500, AD5755_SLEW_RATE_500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ 250, AD5755_SLEW_RATE_250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{ 125, AD5755_SLEW_RATE_125 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ 64, AD5755_SLEW_RATE_64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ 32, AD5755_SLEW_RATE_32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ 16, AD5755_SLEW_RATE_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ 8, AD5755_SLEW_RATE_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ 4, AD5755_SLEW_RATE_4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ 0, AD5755_SLEW_RATE_0_5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const int ad5755_slew_step_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ 256, AD5755_SLEW_STEP_SIZE_256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ 128, AD5755_SLEW_STEP_SIZE_128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ 64, AD5755_SLEW_STEP_SIZE_64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ 32, AD5755_SLEW_STEP_SIZE_32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ 16, AD5755_SLEW_STEP_SIZE_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ 4, AD5755_SLEW_STEP_SIZE_4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ 2, AD5755_SLEW_STEP_SIZE_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ 1, AD5755_SLEW_STEP_SIZE_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ad5755_write_unlocked(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	st->data[0].d32 = cpu_to_be32((reg << 16) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return spi_write(st->spi, &st->data[0].d8[1], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned int channel, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return ad5755_write_unlocked(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ret = ad5755_write_unlocked(indio_dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			.tx_buf = &st->data[0].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			.len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			.cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			.tx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			.rx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			.len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		ret = be32_to_cpu(st->data[1].d32) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	unsigned int channel, unsigned int set, unsigned int clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	st->ctrl[channel] |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	st->ctrl[channel] &= ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		AD5755_CTRL_REG_DAC, st->ctrl[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned int channel, bool pwr_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned int mask = BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if ((bool)(st->pwr_down & mask) == pwr_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!pwr_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		st->pwr_down &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ad5755_update_dac_ctrl(indio_dev, channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		ad5755_update_dac_ctrl(indio_dev, channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			AD5755_DAC_OUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		st->pwr_down |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		ad5755_update_dac_ctrl(indio_dev, channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				AD5755_DAC_DC_DC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const int ad5755_min_max_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	[AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	[AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	[AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	[AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	[AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	[AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void ad5755_get_min_max(struct ad5755_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct iio_chan_spec const *chan, int *min, int *max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	*min = ad5755_min_max_table[mode][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	*max = ad5755_min_max_table[mode][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline int ad5755_get_offset(struct ad5755_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct iio_chan_spec const *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ad5755_get_min_max(st, chan, &min, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return (min * (1 << chan->scan_type.realbits)) / (max - min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int ad5755_chan_reg_info(struct ad5755_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct iio_chan_spec const *chan, long info, bool write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	unsigned int *reg, unsigned int *shift, unsigned int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			*reg = AD5755_WRITE_REG_DATA(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			*reg = AD5755_READ_REG_DATA(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		*shift = chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		*offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			*reg = AD5755_WRITE_REG_OFFSET(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			*reg = AD5755_READ_REG_OFFSET(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		*shift = st->chip_info->calib_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		*offset = 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			*reg =  AD5755_WRITE_REG_GAIN(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			*reg =  AD5755_READ_REG_GAIN(chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		*shift = st->chip_info->calib_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		*offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int ad5755_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	const struct iio_chan_spec *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	unsigned int reg, shift, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	int min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		ad5755_get_min_max(st, chan, &min, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		*val = max - min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		*val = ad5755_get_offset(st, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		ret = ad5755_chan_reg_info(st, chan, info, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 						&reg, &shift, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		ret = ad5755_read(indio_dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		*val = (ret - offset) >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int ad5755_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	const struct iio_chan_spec *chan, int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	unsigned int shift, reg, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ret = ad5755_chan_reg_info(st, chan, info, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 					&reg, &shift, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	val += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (val < 0 || val > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return ad5755_write(indio_dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	const struct iio_chan_spec *chan, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return sprintf(buf, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		       (bool)(st->pwr_down & (1 << chan->channel)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	struct iio_chan_spec const *chan, const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	bool pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	ret = strtobool(buf, &pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct iio_info ad5755_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.read_raw = ad5755_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.write_raw = ad5755_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		.name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.read = ad5755_read_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		.write = ad5755_write_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		.shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define AD5755_CHANNEL(_bits) {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.output = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		BIT(IIO_CHAN_INFO_SCALE) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		BIT(IIO_CHAN_INFO_OFFSET) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		BIT(IIO_CHAN_INFO_CALIBSCALE) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		BIT(IIO_CHAN_INFO_CALIBBIAS),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.realbits = (_bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.storagebits = 16,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.shift = 16 - (_bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.ext_info = ad5755_ext_info,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	[ID_AD5735] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		.channel_template = AD5755_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.has_voltage_out = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.calib_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	[ID_AD5737] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		.channel_template = AD5755_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		.has_voltage_out = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.calib_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	[ID_AD5755] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		.channel_template = AD5755_CHANNEL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.has_voltage_out = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		.calib_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	[ID_AD5757] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		.channel_template = AD5755_CHANNEL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		.has_voltage_out = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		.calib_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	case AD5755_MODE_VOLTAGE_0V_5V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	case AD5755_MODE_VOLTAGE_0V_10V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		return st->chip_info->has_voltage_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	case AD5755_MODE_CURRENT_4mA_20mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	case AD5755_MODE_CURRENT_0mA_20mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	case AD5755_MODE_CURRENT_0mA_24mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int ad5755_setup_pdata(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 			      const struct ad5755_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (pdata->ext_dc_dc_compenstation_resistor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		val |= AD5755_EXT_DC_DC_COMP_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		val = pdata->dac[i].slew.step_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 			AD5755_SLEW_STEP_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		val |= pdata->dac[i].slew.rate <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 			AD5755_SLEW_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		if (pdata->dac[i].slew.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 			val |= AD5755_SLEW_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		ret = ad5755_write_ctrl(indio_dev, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 					AD5755_CTRL_REG_SLEW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		if (!pdata->dac[i].ext_current_sense_resistor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 			val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		if (pdata->dac[i].enable_voltage_overrange)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 			val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		val |= pdata->dac[i].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	case AD5755_MODE_VOLTAGE_0V_5V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	case AD5755_MODE_VOLTAGE_0V_10V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int ad5755_init_channels(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 				const struct ad5755_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	struct ad5755_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	struct iio_chan_spec *channels = st->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		channels[i] = st->chip_info->channel_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		channels[i].channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		channels[i].address = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 			channels[i].type = IIO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 			channels[i].type = IIO_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	indio_dev->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define AD5755_DEFAULT_DAC_PDATA { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		.mode = AD5755_MODE_CURRENT_4mA_20mA, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		.ext_current_sense_resistor = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		.enable_voltage_overrange = false, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		.slew = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 			.enable = false, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 			.rate = AD5755_SLEW_RATE_64k, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 			.step_size = AD5755_SLEW_STEP_SIZE_1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct ad5755_platform_data ad5755_default_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	.ext_dc_dc_compenstation_resistor = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	.dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	.dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	.dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	.dac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		[0] = AD5755_DEFAULT_DAC_PDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		[1] = AD5755_DEFAULT_DAC_PDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 		[2] = AD5755_DEFAULT_DAC_PDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 		[3] = AD5755_DEFAULT_DAC_PDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct ad5755_platform_data *ad5755_parse_dt(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	struct device_node *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	struct ad5755_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	unsigned int tmparray[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	int devnr, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	pdata->ext_dc_dc_compenstation_resistor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	    of_property_read_bool(np, "adi,ext-dc-dc-compenstation-resistor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	if (!of_property_read_u32(np, "adi,dc-dc-phase", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		pdata->dc_dc_phase = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		pdata->dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	pdata->dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	if (!of_property_read_u32(np, "adi,dc-dc-freq-hz", &tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_freq_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 			if (tmp == ad5755_dcdc_freq_table[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 				pdata->dc_dc_freq = ad5755_dcdc_freq_table[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 		if (i == ARRAY_SIZE(ad5755_dcdc_freq_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 			dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 				"adi,dc-dc-freq out of range selecting 410kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	pdata->dc_dc_maxv = AD5755_DC_DC_MAXV_23V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	if (!of_property_read_u32(np, "adi,dc-dc-max-microvolt", &tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 		for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_maxv_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 			if (tmp == ad5755_dcdc_maxv_table[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 				pdata->dc_dc_maxv = ad5755_dcdc_maxv_table[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		if (i == ARRAY_SIZE(ad5755_dcdc_maxv_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 				dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 					"adi,dc-dc-maxv out of range selecting 23V\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	devnr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	for_each_child_of_node(np, pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 		if (devnr >= AD5755_NUM_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 			dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 				"There are too many channels defined in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 			goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 		if (!of_property_read_u32(pp, "adi,mode", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 			pdata->dac[devnr].mode = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 			pdata->dac[devnr].mode = AD5755_MODE_CURRENT_4mA_20mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 		pdata->dac[devnr].ext_current_sense_resistor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 		    of_property_read_bool(pp, "adi,ext-current-sense-resistor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 		pdata->dac[devnr].enable_voltage_overrange =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 		    of_property_read_bool(pp, "adi,enable-voltage-overrange");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 		if (!of_property_read_u32_array(pp, "adi,slew", tmparray, 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 			pdata->dac[devnr].slew.enable = tmparray[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 			pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 			for (i = 0; i < ARRAY_SIZE(ad5755_slew_rate_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 				if (tmparray[1] == ad5755_slew_rate_table[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 					pdata->dac[devnr].slew.rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 						ad5755_slew_rate_table[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 			if (i == ARRAY_SIZE(ad5755_slew_rate_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 				dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 					"channel %d slew rate out of range selecting 64kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 					devnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 			pdata->dac[devnr].slew.step_size = AD5755_SLEW_STEP_SIZE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 			for (i = 0; i < ARRAY_SIZE(ad5755_slew_step_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 				if (tmparray[2] == ad5755_slew_step_table[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 					pdata->dac[devnr].slew.step_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 						ad5755_slew_step_table[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 			if (i == ARRAY_SIZE(ad5755_slew_step_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 				dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 					"channel %d slew step size out of range selecting 1 LSB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 					devnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 			pdata->dac[devnr].slew.enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 			pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 			pdata->dac[devnr].slew.step_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 			    AD5755_SLEW_STEP_SIZE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 		devnr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)  error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	devm_kfree(dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct ad5755_platform_data *ad5755_parse_dt(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int ad5755_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	enum ad5755_type type = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	const struct ad5755_platform_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	struct ad5755_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 	if (indio_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 		dev_err(&spi->dev, "Failed to allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 		return  -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 	st->chip_info = &ad5755_chip_info_tbl[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 	st->pwr_down = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	indio_dev->info = &ad5755_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	indio_dev->num_channels = AD5755_NUM_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	if (spi->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 		pdata = ad5755_parse_dt(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 		pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 		dev_warn(&spi->dev, "no platform data? using default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 		pdata = &ad5755_default_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	ret = ad5755_init_channels(indio_dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 	ret = ad5755_setup_pdata(indio_dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct spi_device_id ad5755_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 	{ "ad5755", ID_AD5755 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 	{ "ad5755-1", ID_AD5755 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	{ "ad5757", ID_AD5757 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 	{ "ad5735", ID_AD5735 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 	{ "ad5737", ID_AD5737 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) MODULE_DEVICE_TABLE(spi, ad5755_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const struct of_device_id ad5755_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	{ .compatible = "adi,ad5755" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	{ .compatible = "adi,ad5755-1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	{ .compatible = "adi,ad5757" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	{ .compatible = "adi,ad5735" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	{ .compatible = "adi,ad5737" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) MODULE_DEVICE_TABLE(of, ad5755_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct spi_driver ad5755_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 		.name = "ad5755",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	.probe = ad5755_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 	.id_table = ad5755_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) module_spi_driver(ad5755_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) MODULE_LICENSE("GPL v2");