^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is part of AD5686 DAC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DRIVERS_IIO_DAC_AD5686_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DRIVERS_IIO_DAC_AD5686_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AD5310_CMD(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AD5683_DATA(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AD5686_ADDR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AD5686_CMD(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AD5686_ADDR_DAC(chan) (0x1 << (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD5686_ADDR_ALL_DAC 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD5686_CMD_NOOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD5686_CMD_WRITE_INPUT_N 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AD5686_CMD_UPDATE_DAC_N 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD5686_CMD_POWERDOWN_DAC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD5686_CMD_LDAC_MASK 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD5686_CMD_RESET 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD5686_CMD_READBACK_ENABLE 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD5686_LDAC_PWRDN_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD5686_LDAC_PWRDN_1K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD5686_LDAC_PWRDN_100K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD5686_LDAC_PWRDN_3STATE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD5686_CMD_CONTROL_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD5686_CMD_READBACK_ENABLE_V2 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD5310_REF_BIT_MSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD5683_REF_BIT_MSK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD5693_REF_BIT_MSK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * ad5686_supported_device_ids:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum ad5686_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ID_AD5310R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ID_AD5311R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ID_AD5671R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ID_AD5672R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ID_AD5674R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ID_AD5675R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ID_AD5676,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ID_AD5676R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ID_AD5679R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ID_AD5681R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ID_AD5682R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ID_AD5683,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ID_AD5683R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ID_AD5684,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ID_AD5684R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ID_AD5685R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ID_AD5686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ID_AD5686R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ID_AD5691R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ID_AD5692R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ID_AD5693,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ID_AD5693R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ID_AD5694,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ID_AD5694R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ID_AD5695R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ID_AD5696,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ID_AD5696R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum ad5686_regmap_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) AD5310_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AD5683_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AD5693_REGMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ad5686_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) typedef int (*ad5686_write_func)(struct ad5686_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 cmd, u8 addr, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * struct ad5686_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @int_vref_mv: AD5620/40/60: the internal reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @num_channels: number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @channel: channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @regmap_type: register map layout variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ad5686_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum ad5686_regmap_type regmap_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * struct ad5446_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @spi: spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @chip_info: chip model specific constants, available modes etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @reg: supply regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @vref_mv: actual reference voltage used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @pwr_down_mask: power down mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @pwr_down_mode: current power down mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @use_internal_vref: set to true if the internal reference voltage is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @lock lock to protect the data buffer during regmap ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @data: spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ad5686_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct ad5686_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned short vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int pwr_down_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int pwr_down_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ad5686_write_func write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ad5686_read_func read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bool use_internal_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __be16 d16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } data[3] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ad5686_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum ad5686_supported_device_ids chip_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char *name, ad5686_write_func write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ad5686_read_func read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ad5686_remove(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif /* __DRIVERS_IIO_DAC_AD5686_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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