Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD5686R, AD5685R, AD5684R Digital to analog converters  driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "ad5686.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static const char * const ad5686_powerdown_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	"1kohm_to_gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	"100kohm_to_gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	"three_state"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 				     const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 				     const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 				     unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static const struct iio_enum ad5686_powerdown_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.items = ad5686_powerdown_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.get = ad5686_get_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.set = ad5686_set_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		uintptr_t private, const struct iio_chan_spec *chan, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				       (0x3 << (chan->channel * 2))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 					  uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 					  const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					  const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 					  size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	bool readin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned int val, ref_bit_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8 shift, address = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ret = strtobool(buf, &readin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (readin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		st->pwr_down_mask |= (0x3 << (chan->channel * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	switch (st->chip_info->regmap_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case AD5310_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		shift = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		ref_bit_msk = AD5310_REF_BIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case AD5683_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		shift = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		ref_bit_msk = AD5683_REF_BIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case AD5686_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		ref_bit_msk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		/* AD5674R/AD5679R have 16 channels and 2 powerdown registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (chan->channel > 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			address = 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case AD5693_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		shift = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		ref_bit_msk = AD5693_REF_BIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	val = ((st->pwr_down_mask & st->pwr_down_mode) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!st->use_internal_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		val |= ref_bit_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = st->write(st, AD5686_CMD_POWERDOWN_DAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			address, val >> (address * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int ad5686_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			   int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			   int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			   long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		ret = st->read(st, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		*val = (ret >> chan->scan_type.shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			GENMASK(chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		*val = st->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int ad5686_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			    int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			    int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			    long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (val > (1 << chan->scan_type.realbits) || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		ret = st->write(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				chan->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				val << chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct iio_info ad5686_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.read_raw = ad5686_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.write_raw = ad5686_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.read = ad5686_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.write = ad5686_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AD5868_CHANNEL(chan, addr, bits, _shift) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.output = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.channel = chan,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.address = addr,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.scan_type = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			.sign = 'u',				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			.realbits = (bits),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			.storagebits = 16,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			.shift = (_shift),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		},						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.ext_info = ad5686_ext_info,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DECLARE_AD5693_CHANNELS(name, bits, _shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct iio_chan_spec name[] = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		AD5868_CHANNEL(0, 0, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DECLARE_AD5686_CHANNELS(name, bits, _shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct iio_chan_spec name[] = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		AD5868_CHANNEL(0, 1, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		AD5868_CHANNEL(1, 2, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		AD5868_CHANNEL(2, 4, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		AD5868_CHANNEL(3, 8, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DECLARE_AD5676_CHANNELS(name, bits, _shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct iio_chan_spec name[] = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		AD5868_CHANNEL(0, 0, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		AD5868_CHANNEL(1, 1, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		AD5868_CHANNEL(2, 2, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		AD5868_CHANNEL(3, 3, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		AD5868_CHANNEL(4, 4, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		AD5868_CHANNEL(5, 5, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		AD5868_CHANNEL(6, 6, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		AD5868_CHANNEL(7, 7, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DECLARE_AD5679_CHANNELS(name, bits, _shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct iio_chan_spec name[] = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		AD5868_CHANNEL(0, 0, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		AD5868_CHANNEL(1, 1, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		AD5868_CHANNEL(2, 2, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		AD5868_CHANNEL(3, 3, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		AD5868_CHANNEL(4, 4, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		AD5868_CHANNEL(5, 5, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		AD5868_CHANNEL(6, 6, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		AD5868_CHANNEL(7, 7, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		AD5868_CHANNEL(8, 8, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		AD5868_CHANNEL(9, 9, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		AD5868_CHANNEL(10, 10, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		AD5868_CHANNEL(11, 11, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		AD5868_CHANNEL(12, 12, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		AD5868_CHANNEL(13, 13, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		AD5868_CHANNEL(14, 14, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		AD5868_CHANNEL(15, 15, bits, _shift),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	[ID_AD5310R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.channels = ad5310r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.regmap_type = AD5310_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	[ID_AD5311R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.channels = ad5311r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.regmap_type = AD5693_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	[ID_AD5671R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.channels = ad5672_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[ID_AD5672R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.channels = ad5672_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	[ID_AD5674R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.channels = ad5674r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.num_channels = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	[ID_AD5675R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.channels = ad5676_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	[ID_AD5676] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.channels = ad5676_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	[ID_AD5676R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.channels = ad5676_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	[ID_AD5679R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.channels = ad5679r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.num_channels = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	[ID_AD5681R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.channels = ad5691r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.regmap_type = AD5683_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	[ID_AD5682R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.channels = ad5692r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.regmap_type = AD5683_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	[ID_AD5683] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		.channels = ad5693_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.regmap_type = AD5683_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	[ID_AD5683R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.channels = ad5693_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.regmap_type = AD5683_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	[ID_AD5684] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.channels = ad5684_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	[ID_AD5684R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.channels = ad5684_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	[ID_AD5685R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.channels = ad5685r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	[ID_AD5686] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.channels = ad5686_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	[ID_AD5686R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.channels = ad5686_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	[ID_AD5691R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.channels = ad5691r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.regmap_type = AD5693_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	[ID_AD5692R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.channels = ad5692r_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.regmap_type = AD5693_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	[ID_AD5693] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		.channels = ad5693_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.regmap_type = AD5693_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	[ID_AD5693R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		.channels = ad5693_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		.regmap_type = AD5693_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	[ID_AD5694] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.channels = ad5684_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	[ID_AD5694R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		.channels = ad5684_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	[ID_AD5696] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.channels = ad5686_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	[ID_AD5696R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.channels = ad5686_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		.regmap_type = AD5686_REGMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ad5686_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		 enum ad5686_supported_device_ids chip_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		 const char *name, ad5686_write_func write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		 ad5686_read_func read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	struct ad5686_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	unsigned int val, ref_bit_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	int ret, i, voltage_uv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return  -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	dev_set_drvdata(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	st->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	st->write = write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	st->read = read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	st->reg = devm_regulator_get_optional(dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (!IS_ERR(st->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		ret = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 			goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		voltage_uv = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	st->chip_info = &ad5686_chip_info_tbl[chip_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (voltage_uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		st->vref_mv = voltage_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		st->vref_mv = st->chip_info->int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	/* Set all the power down mode for all channels to 1K pulldown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	for (i = 0; i < st->chip_info->num_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		st->pwr_down_mode |= (0x01 << (i * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	indio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	indio_dev->info = &ad5686_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	switch (st->chip_info->regmap_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	case AD5310_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		cmd = AD5686_CMD_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		ref_bit_msk = AD5310_REF_BIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		st->use_internal_vref = !voltage_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	case AD5683_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		cmd = AD5686_CMD_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		ref_bit_msk = AD5683_REF_BIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		st->use_internal_vref = !voltage_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	case AD5686_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		cmd = AD5686_CMD_INTERNAL_REFER_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		ref_bit_msk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	case AD5693_REGMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		cmd = AD5686_CMD_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		ref_bit_msk = AD5693_REF_BIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		st->use_internal_vref = !voltage_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	val = (voltage_uv | ref_bit_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	ret = st->write(st, cmd, 0, !!val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	if (!IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) EXPORT_SYMBOL_GPL(ad5686_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ad5686_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	struct ad5686_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (!IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EXPORT_SYMBOL_GPL(ad5686_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_LICENSE("GPL v2");