^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD5624R SPI DAC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010-2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef SPI_AD5624R_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define SPI_AD5624R_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AD5624R_DAC_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AD5624R_ADDR_DAC0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AD5624R_ADDR_DAC1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AD5624R_ADDR_DAC2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AD5624R_ADDR_DAC3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AD5624R_ADDR_ALL_DAC 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AD5624R_CMD_WRITE_INPUT_N 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AD5624R_CMD_UPDATE_DAC_N 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_N 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AD5624R_CMD_POWERDOWN_DAC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AD5624R_CMD_RESET 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD5624R_CMD_LDAC_SETUP 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AD5624R_CMD_INTERNAL_REFER_SETUP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD5624R_LDAC_PWRDN_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AD5624R_LDAC_PWRDN_1K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD5624R_LDAC_PWRDN_100K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD5624R_LDAC_PWRDN_3STATE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * struct ad5624r_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @channels: channel spec for the DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @int_vref_mv: AD5620/40/60: the internal reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ad5624r_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * struct ad5446_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @indio_dev: the industrial I/O device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @us: spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @chip_info: chip model specific constants, available modes etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @reg: supply regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @vref_mv: actual reference voltage used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @pwr_down_mask power down mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @pwr_down_mode current power down mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct ad5624r_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct spi_device *us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct ad5624r_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned short vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned pwr_down_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned pwr_down_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * ad5624r_supported_device_ids:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The AD5624/44/64 parts are available in different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * fixed internal reference voltage options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum ad5624r_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ID_AD5624R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ID_AD5644R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ID_AD5664R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ID_AD5624R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ID_AD5644R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ID_AD5664R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif /* SPI_AD5624R_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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