^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD5592R Digital <-> Analog converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014-2016 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Paul Cercueil <paul.cercueil@analog.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/iio/adi,ad5592r.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ad5592r-base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct ad5592r_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mutex_lock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (st->gpio_out & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) val = st->gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ret = st->ops->gpio_read(st, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) mutex_unlock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return !!(val & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct ad5592r_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mutex_lock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) st->gpio_val |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) st->gpio_val &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mutex_unlock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ad5592r_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mutex_lock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) st->gpio_out &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) st->gpio_in |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mutex_unlock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ad5592r_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mutex_lock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) st->gpio_val |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) st->gpio_val &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) st->gpio_in &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) st->gpio_out |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mutex_unlock(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ad5592r_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!(st->gpio_map & BIT(offset))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int ad5592r_gpio_init(struct ad5592r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!st->gpio_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) st->gpiochip.label = dev_name(st->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) st->gpiochip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) st->gpiochip.ngpio = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) st->gpiochip.parent = st->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) st->gpiochip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) st->gpiochip.direction_input = ad5592r_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) st->gpiochip.direction_output = ad5592r_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) st->gpiochip.get = ad5592r_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) st->gpiochip.set = ad5592r_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) st->gpiochip.request = ad5592r_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) st->gpiochip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mutex_init(&st->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return gpiochip_add_data(&st->gpiochip, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (st->gpio_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) gpiochip_remove(&st->gpiochip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int ad5592r_reset(struct ad5592r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct gpio_desc *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) gpiod_set_value(gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Writing this magic value resets the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int ad5592r_get_vref(struct ad5592r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (st->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int ad5592r_set_channel_modes(struct ad5592r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const struct ad5592r_rw_ops *ops = st->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u16 read_back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (i = 0; i < st->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) switch (st->channel_modes[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case CH_MODE_DAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dac |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case CH_MODE_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) adc |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case CH_MODE_DAC_AND_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dac |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) adc |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case CH_MODE_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) st->gpio_map |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) st->gpio_in |= BIT(i); /* Default to input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case CH_MODE_UNUSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (st->channel_offstate[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case CH_OFFSTATE_OUT_TRISTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tristate |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case CH_OFFSTATE_OUT_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) st->gpio_out |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case CH_OFFSTATE_OUT_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) st->gpio_out |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) st->gpio_val |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case CH_OFFSTATE_PULLDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pulldown |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Pull down unused pins to GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Configure pins that we use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Verify that we can read back at least one register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!ret && (read_back & 0xff) != adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) st->channel_modes[i] = CH_MODE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ad5592r_set_channel_modes(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int ad5592r_write_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct ad5592r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (val >= (1 << chan->scan_type.realbits) || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!chan->output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = st->ops->write_dac(st, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) st->cached_dac[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (chan->type == IIO_VOLTAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bool gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (val == st->scale_avail[0][0] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val2 == st->scale_avail[0][1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) gain = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else if (val == st->scale_avail[1][0] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val2 == st->scale_avail[1][1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) gain = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &st->cached_gp_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (chan->output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) st->cached_gp_ctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AD5592R_REG_CTRL_DAC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) st->cached_gp_ctrl &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ~AD5592R_REG_CTRL_DAC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) st->cached_gp_ctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) AD5592R_REG_CTRL_ADC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) st->cached_gp_ctrl &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ~AD5592R_REG_CTRL_ADC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) st->cached_gp_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int ad5592r_read_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct ad5592r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u16 read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret, mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!chan->output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = st->ops->read_adc(st, chan->channel, &read_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(st->dev, "Error while reading channel %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) read_val &= GENMASK(11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) read_val = st->cached_dac[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) chan->channel, read_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *val = (int) read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *val = ad5592r_get_vref(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) s64 tmp = *val * (3767897513LL / 25LL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *val = div_s64_rem(tmp, 1000000000LL, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (chan->output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mult = !!(st->cached_gp_ctrl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) AD5592R_REG_CTRL_DAC_RANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mult = !!(st->cached_gp_ctrl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) AD5592R_REG_CTRL_ADC_RANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *val *= ++mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = ad5592r_get_vref(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *val = (-34365 * 25) / ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *val = (-75365 * 25) / ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct iio_chan_spec const *chan, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct iio_info ad5592r_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .read_raw = ad5592r_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .write_raw = ad5592r_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct ad5592r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return sprintf(buf, "%d.%09u %d.%09u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) st->scale_avail[0][0], st->scale_avail[0][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) st->scale_avail[1][0], st->scale_avail[1][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .name = "scale_available",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .read = ad5592r_show_scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .shared = IIO_SHARED_BY_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void ad5592r_setup_channel(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct iio_chan_spec *chan, bool output, unsigned id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) chan->type = IIO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) chan->indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) chan->output = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) chan->channel = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) chan->scan_type.sign = 'u';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) chan->scan_type.realbits = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) chan->scan_type.storagebits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) chan->ext_info = ad5592r_ext_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct ad5592r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned i, curr_channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) num_channels = st->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct fwnode_handle *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 reg, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) device_for_each_child_node(st->dev, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = fwnode_property_read_u32(child, "reg", ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret || reg >= ARRAY_SIZE(st->channel_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) st->channel_modes[reg] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) fwnode_property_read_u32(child, "adi,off-state", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) st->channel_offstate[reg] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) channels = devm_kcalloc(st->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 1 + 2 * num_channels, sizeof(*channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) switch (st->channel_modes[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case CH_MODE_DAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ad5592r_setup_channel(iio_dev, &channels[curr_channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) true, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) curr_channel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case CH_MODE_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ad5592r_setup_channel(iio_dev, &channels[curr_channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) false, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) curr_channel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case CH_MODE_DAC_AND_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ad5592r_setup_channel(iio_dev, &channels[curr_channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) true, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) curr_channel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ad5592r_setup_channel(iio_dev, &channels[curr_channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) false, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) curr_channel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) channels[curr_channel].type = IIO_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) channels[curr_channel].channel = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) BIT(IIO_CHAN_INFO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) curr_channel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) iio_dev->num_channels = curr_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) iio_dev->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) st->scale_avail[0][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) st->scale_avail[1][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ad5592r_probe(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) const struct ad5592r_rw_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct iio_dev *iio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct ad5592r_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) st->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) st->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) st->num_channels = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_set_drvdata(dev, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) st->reg = devm_regulator_get_optional(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (IS_ERR(st->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) st->reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) iio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) iio_dev->info = &ad5592r_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) iio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ad5592r_init_scales(st, ad5592r_get_vref(st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = ad5592r_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = ops->reg_write(st, AD5592R_REG_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = ad5592r_alloc_channels(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = ad5592r_set_channel_modes(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto error_reset_ch_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = iio_device_register(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) goto error_reset_ch_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = ad5592r_gpio_init(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto error_dev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) error_dev_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) iio_device_unregister(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) error_reset_ch_modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ad5592r_reset_channel_modes(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (st->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) EXPORT_SYMBOL_GPL(ad5592r_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int ad5592r_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct iio_dev *iio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct ad5592r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) iio_device_unregister(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ad5592r_reset_channel_modes(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ad5592r_gpio_cleanup(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (st->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) EXPORT_SYMBOL_GPL(ad5592r_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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