Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD5415, AD5426, AD5429, AD5432, AD5439, AD5443, AD5449 Digital to Analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Converter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_data/ad5449.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AD5449_MAX_CHANNELS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD5449_MAX_VREFS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD5449_CMD_NOOP			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AD5449_CMD_LOAD_AND_UPDATE(x)	(0x1 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD5449_CMD_READ(x)		(0x2 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD5449_CMD_LOAD(x)		(0x3 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD5449_CMD_CTRL			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD5449_CTRL_SDO_OFFSET		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AD5449_CTRL_DAISY_CHAIN		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AD5449_CTRL_HCLR_TO_MIDSCALE	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AD5449_CTRL_SAMPLE_RISING	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * struct ad5449_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @channels:		Channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @num_channels:	Number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @has_ctrl:		Chip has a control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct ad5449_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	bool has_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * struct ad5449 - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @spi:		the SPI device for this driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @chip_info:		chip model specific constants, available modes etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @vref_reg:		vref supply regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @has_sdo:		whether the SDO line is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @dac_cache:		Cache for the DAC values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @data:		spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @lock:		lock to protect the data buffer during SPI ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct ad5449 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	const struct ad5449_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct regulator_bulk_data	vref_reg[AD5449_MAX_VREFS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct mutex			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	bool has_sdo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	uint16_t dac_cache[AD5449_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__be16 data[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) enum ad5449_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ID_AD5426,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ID_AD5429,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ID_AD5432,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ID_AD5439,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ID_AD5443,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ID_AD5449,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int ad5449_write(struct iio_dev *indio_dev, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct ad5449 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	st->data[0] = cpu_to_be16((addr << 12) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ret = spi_write(st->spi, st->data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct ad5449 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			.tx_buf = &st->data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			.cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			.tx_buf = &st->data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			.rx_buf = &st->data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	st->data[0] = cpu_to_be16(addr << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	st->data[1] = cpu_to_be16(AD5449_CMD_NOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	*val = be16_to_cpu(st->data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int ad5449_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct iio_chan_spec const *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct ad5449 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct regulator_bulk_data *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (st->has_sdo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			ret = ad5449_read(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				AD5449_CMD_READ(chan->address), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			*val &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			*val = st->dac_cache[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		reg = &st->vref_reg[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		scale_uv = regulator_get_voltage(reg->consumer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (scale_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			return scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		*val = scale_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ad5449_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct iio_chan_spec const *chan, int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct ad5449 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (val < 0 || val >= (1 << chan->scan_type.realbits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		ret = ad5449_write(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			AD5449_CMD_LOAD_AND_UPDATE(chan->address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			val << chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			st->dac_cache[chan->address] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct iio_info ad5449_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.read_raw = ad5449_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.write_raw = ad5449_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AD5449_CHANNEL(chan, bits) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.output = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.channel = (chan),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		BIT(IIO_CHAN_INFO_SCALE),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.address = (chan),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.realbits = (bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.storagebits = 16,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.shift = 12 - (bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DECLARE_AD5449_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const struct iio_chan_spec name[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	AD5449_CHANNEL(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	AD5449_CHANNEL(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static DECLARE_AD5449_CHANNELS(ad5429_channels, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static DECLARE_AD5449_CHANNELS(ad5439_channels, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static DECLARE_AD5449_CHANNELS(ad5449_channels, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct ad5449_chip_info ad5449_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	[ID_AD5426] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.channels = ad5429_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.has_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	[ID_AD5429] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.channels = ad5429_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.has_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	[ID_AD5432] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.channels = ad5439_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.has_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	[ID_AD5439] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.channels = ad5439_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.has_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	[ID_AD5443] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.channels = ad5449_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.has_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	[ID_AD5449] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.channels = ad5449_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.has_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const char *ad5449_vref_name(struct ad5449 *st, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (st->chip_info->num_channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return "VREF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return "VREFA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return "VREFB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int ad5449_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct ad5449_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct ad5449 *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	st->chip_info = &ad5449_chip_info[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	for (i = 0; i < st->chip_info->num_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		st->vref_reg[i].supply = ad5449_vref_name(st, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = devm_regulator_bulk_get(&spi->dev, st->chip_info->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ret = regulator_bulk_enable(st->chip_info->num_channels, st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	indio_dev->info = &ad5449_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (st->chip_info->has_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		unsigned int ctrl = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			if (pdata->hardware_clear_to_midscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				ctrl |= AD5449_CTRL_HCLR_TO_MIDSCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			ctrl |= pdata->sdo_mode << AD5449_CTRL_SDO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			st->has_sdo = pdata->sdo_mode != AD5449_SDO_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			st->has_sdo = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ad5449_write(indio_dev, AD5449_CMD_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int ad5449_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct ad5449 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct spi_device_id ad5449_spi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	{ "ad5415", ID_AD5449 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	{ "ad5426", ID_AD5426 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	{ "ad5429", ID_AD5429 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{ "ad5432", ID_AD5432 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ "ad5439", ID_AD5439 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	{ "ad5443", ID_AD5443 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{ "ad5449", ID_AD5449 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_DEVICE_TABLE(spi, ad5449_spi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct spi_driver ad5449_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.name = "ad5449",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.probe = ad5449_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.remove = ad5449_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.id_table = ad5449_spi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) module_spi_driver(ad5449_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_DESCRIPTION("Analog Devices AD5449 and similar DACs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_LICENSE("GPL v2");