^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD5421 Digital to analog converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/dac/ad5421.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD5421_REG_DAC_DATA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AD5421_REG_CTRL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD5421_REG_OFFSET 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD5421_REG_GAIN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* load dac and fault shared the same register number. Writing to it will cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * a dac load command, reading from it will return the fault status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD5421_REG_LOAD_DAC 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD5421_REG_FAULT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD5421_REG_FORCE_ALARM_CURRENT 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD5421_REG_RESET 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD5421_REG_START_CONVERSION 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD5421_REG_NOOP 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD5421_CTRL_WATCHDOG_DISABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD5421_CTRL_MIN_CURRENT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD5421_CTRL_ADC_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD5421_CTRL_PWR_DOWN_INT_VREF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD5421_FAULT_SPI BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD5421_FAULT_PEC BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD5421_FAULT_OVER_CURRENT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD5421_FAULT_UNDER_CURRENT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AD5421_FAULT_TEMP_OVER_140 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AD5421_FAULT_TEMP_OVER_100 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AD5421_FAULT_UNDER_VOLTAGE_6V BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AD5421_FAULT_UNDER_VOLTAGE_12V BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* These bits will cause the fault pin to go high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD5421_FAULT_TRIGGER_IRQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (AD5421_FAULT_SPI | AD5421_FAULT_PEC | AD5421_FAULT_OVER_CURRENT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) AD5421_FAULT_UNDER_CURRENT | AD5421_FAULT_TEMP_OVER_140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct ad5421_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @spi: spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @ctrl: control register cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @current_range: current range which the device is configured for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @data: spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @fault_mask: software masking of events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @lock: lock to protect the data buffer during SPI ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ad5421_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum ad5421_current_range current_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int fault_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } data[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct iio_event_spec ad5421_current_event[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct iio_event_spec ad5421_temp_event[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct iio_chan_spec ad5421_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .type = IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .output = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .event_spec = ad5421_current_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_event_specs = ARRAY_SIZE(ad5421_current_event),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .channel = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .event_spec = ad5421_temp_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .num_event_specs = ARRAY_SIZE(ad5421_temp_event),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int ad5421_write_unlocked(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) st->data[0].d32 = cpu_to_be32((reg << 16) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return spi_write(st->spi, &st->data[0].d8[1], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = ad5421_write_unlocked(indio_dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .tx_buf = &st->data[0].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .rx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = be32_to_cpu(st->data[1].d32) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) st->ctrl &= ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) st->ctrl |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static irqreturn_t ad5421_fault_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int old_fault = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* If we had a fault, this might mean that the DAC has lost its state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * and has been reset. Make sure that the control register actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * contains what we expect it to contain. Otherwise the watchdog might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * be enabled and we get watchdog timeout faults, which will render the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * DAC unusable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ad5421_update_ctrl(indio_dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* The fault pin stays high as long as a fault condition is present and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * it is not possible to mask fault conditions. For certain fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * conditions for example like over-temperature it takes some time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * until the fault condition disappears. If we would exit the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * handler immediately after handling the event it would be entered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * again instantly. Thus we fall back to polling in case we detect that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * a interrupt condition is still present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* 0xffff is a invalid value for the register and will only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * read if there has been a communication error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (fault == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fault = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* we are only interested in new events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) events = (old_fault ^ fault) & fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) events &= st->fault_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (events & AD5421_FAULT_OVER_CURRENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (events & AD5421_FAULT_UNDER_CURRENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (events & AD5421_FAULT_TEMP_OVER_140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IIO_UNMOD_EVENT_CODE(IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) old_fault = fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* still active? go to sleep for some time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (fault & AD5421_FAULT_TRIGGER_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } while (fault & AD5421_FAULT_TRIGGER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void ad5421_get_current_min_max(struct ad5421_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int *min, unsigned int *max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* The current range is configured using external pins, which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * usually hard-wired and not run-time switchable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) switch (st->current_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case AD5421_CURRENT_RANGE_4mA_20mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *min = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *max = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case AD5421_CURRENT_RANGE_3mA8_21mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *min = 3800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *max = 21000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case AD5421_CURRENT_RANGE_3mA2_24mA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *min = 3200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *max = 24000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline unsigned int ad5421_get_offset(struct ad5421_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ad5421_get_current_min_max(st, &min, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return (min * (1 << 16)) / (max - min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int ad5421_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct iio_chan_spec const *chan, int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (chan->type != IIO_CURRENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ad5421_get_current_min_max(st, &min, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *val = max - min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *val2 = (1 << 16) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *val = ad5421_get_offset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = ad5421_read(indio_dev, AD5421_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *val = ret - 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = ad5421_read(indio_dev, AD5421_REG_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int ad5421_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const unsigned int max_val = 1 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val += 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ad5421_write(indio_dev, AD5421_REG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ad5421_write(indio_dev, AD5421_REG_GAIN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int ad5421_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mask = AD5421_FAULT_OVER_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mask = AD5421_FAULT_UNDER_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mask = AD5421_FAULT_TEMP_OVER_140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) st->fault_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) st->fault_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int ad5421_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct ad5421_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mask = AD5421_FAULT_OVER_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mask = AD5421_FAULT_UNDER_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mask = AD5421_FAULT_TEMP_OVER_140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return (bool)(st->fault_mask & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int ad5421_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) enum iio_event_direction dir, enum iio_event_info info, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *val = 140000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct iio_info ad5421_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .read_raw = ad5421_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .write_raw = ad5421_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .read_event_config = ad5421_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .write_event_config = ad5421_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .read_event_value = ad5421_read_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int ad5421_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct ad5421_platform_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct ad5421_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (indio_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(&spi->dev, "Failed to allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) indio_dev->name = "ad5421";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) indio_dev->info = &ad5421_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) indio_dev->channels = ad5421_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) indio_dev->num_channels = ARRAY_SIZE(ad5421_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) AD5421_CTRL_AUTO_FAULT_READBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) st->current_range = pdata->current_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (pdata->external_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) st->ctrl |= AD5421_CTRL_PWR_DOWN_INT_VREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) st->current_range = AD5421_CURRENT_RANGE_4mA_20mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* write initial ctrl register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ad5421_update_ctrl(indio_dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = devm_request_threaded_irq(&spi->dev, spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ad5421_fault_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "ad5421 fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct spi_driver ad5421_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "ad5421",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .probe = ad5421_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) module_spi_driver(ad5421_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_DESCRIPTION("Analog Devices AD5421 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_ALIAS("spi:ad5421");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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