^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * multi-channel Digital to Analog Converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AD5360_CMD(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AD5360_ADDR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD5360_READBACK_TYPE(x) ((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AD5360_READBACK_ADDR(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD5360_CMD_WRITE_DATA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD5360_CMD_WRITE_OFFSET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD5360_CMD_WRITE_GAIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD5360_CMD_SPECIAL_FUNCTION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Special function register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD5360_REG_SF_NOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD5360_REG_SF_CTRL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD5360_REG_SF_OFS(x) (0x2 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD5360_REG_SF_READBACK 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD5360_SF_CTRL_PWR_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD5360_READBACK_X1A 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD5360_READBACK_X1B 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD5360_READBACK_OFFSET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD5360_READBACK_GAIN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD5360_READBACK_SF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * struct ad5360_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @channel_template: channel specification template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @num_channels: number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @channels_per_group: number of channels per group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @num_vrefs: number of vref supplies for the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct ad5360_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct iio_chan_spec channel_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int channels_per_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int num_vrefs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * struct ad5360_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @spi: spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @chip_info: chip model specific constants, available modes etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @vref_reg: vref supply regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @ctrl: control register cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @lock: lock to protect the data buffer during SPI ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @data: spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct ad5360_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const struct ad5360_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regulator_bulk_data vref_reg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 d8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } data[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum ad5360_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ID_AD5360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ID_AD5361,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ID_AD5362,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ID_AD5363,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ID_AD5370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ID_AD5371,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ID_AD5372,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ID_AD5373,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AD5360_CHANNEL(bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BIT(IIO_CHAN_INFO_OFFSET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) BIT(IIO_CHAN_INFO_CALIBSCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BIT(IIO_CHAN_INFO_CALIBBIAS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .realbits = (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .shift = 16 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [ID_AD5360] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .channel_template = AD5360_CHANNEL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .num_channels = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .channels_per_group = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [ID_AD5361] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .channel_template = AD5360_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_channels = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .channels_per_group = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [ID_AD5362] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .channel_template = AD5360_CHANNEL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .channels_per_group = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [ID_AD5363] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .channel_template = AD5360_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .channels_per_group = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [ID_AD5370] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .channel_template = AD5360_CHANNEL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .num_channels = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .channels_per_group = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [ID_AD5371] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .channel_template = AD5360_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .num_channels = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .channels_per_group = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .num_vrefs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [ID_AD5372] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .channel_template = AD5360_CHANNEL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .num_channels = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .channels_per_group = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [ID_AD5373] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .channel_template = AD5360_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .num_channels = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .channels_per_group = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .num_vrefs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* The first groups have their own vref, while the remaining groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * share the last vref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) i = channel / st->chip_info->channels_per_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (i >= st->chip_info->num_vrefs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) i = st->chip_info->num_vrefs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int ad5360_get_channel_vref(struct ad5360_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int i = ad5360_get_channel_vref_index(st, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return regulator_get_voltage(st->vref_reg[i].consumer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int ad5360_write_unlocked(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int cmd, unsigned int addr, unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) st->data[0].d32 = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return spi_write(st->spi, &st->data[0].d8[1], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int addr, unsigned int val, unsigned int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .tx_buf = &st->data[0].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .rx_buf = &st->data[1].d8[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) AD5360_ADDR(AD5360_REG_SF_READBACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) AD5360_READBACK_TYPE(type) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) AD5360_READBACK_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = be32_to_cpu(st->data[1].d32) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static ssize_t ad5360_read_dac_powerdown(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return sprintf(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) st->ctrl |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) st->ctrl &= ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) AD5360_REG_SF_CTRL, st->ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static ssize_t ad5360_write_dac_powerdown(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct device_attribute *attr, const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bool pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = strtobool(buf, &pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (pwr_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static IIO_DEVICE_ATTR(out_voltage_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ad5360_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ad5360_write_dac_powerdown, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct attribute *ad5360_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct attribute_group ad5360_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .attrs = ad5360_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int ad5360_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int max_val = (1 << chan->scan_type.realbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int ofs_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) chan->address, val, chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) chan->address, val, chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (val >= max_val || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) chan->address, val, chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (val <= -max_val || val > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) val = -val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* offset is supposed to have the same scale as raw, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * is always 14bits wide, so on a chip where the raw value has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * more bits, we need to shift offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val >>= (chan->scan_type.realbits - 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* There is one DAC offset register per vref. Changing one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * channels offset will also change the offset for all other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * channels which share the same vref supply. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) AD5360_REG_SF_OFS(ofs_index), val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int ad5360_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int ofs_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *val = ret >> chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) scale_uv = ad5360_get_channel_vref(st, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (scale_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* vout = 4 * vref * dac_code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *val = scale_uv * 4 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) AD5360_REG_SF_OFS(ofs_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret <<= (chan->scan_type.realbits - 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *val = -ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct iio_info ad5360_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .read_raw = ad5360_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .write_raw = ad5360_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .attrs = &ad5360_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const ad5360_vref_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "vref0", "vref1", "vref2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int ad5360_alloc_channels(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) channels = kcalloc(st->chip_info->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sizeof(struct iio_chan_spec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (i = 0; i < st->chip_info->num_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) channels[i] = st->chip_info->channel_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) channels[i].channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) channels[i].address = AD5360_CHAN_ADDR(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) indio_dev->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int ad5360_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) enum ad5360_type type = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct ad5360_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (indio_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(&spi->dev, "Failed to allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) st->chip_info = &ad5360_chip_info_tbl[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) indio_dev->info = &ad5360_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = ad5360_alloc_channels(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (i = 0; i < st->chip_info->num_vrefs; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) st->vref_reg[i].supply = ad5360_vref_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto error_free_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto error_free_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) error_free_channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) kfree(indio_dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int ad5360_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct ad5360_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) kfree(indio_dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct spi_device_id ad5360_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { "ad5360", ID_AD5360 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { "ad5361", ID_AD5361 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { "ad5362", ID_AD5362 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { "ad5363", ID_AD5363 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { "ad5370", ID_AD5370 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { "ad5371", ID_AD5371 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { "ad5372", ID_AD5372 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { "ad5373", ID_AD5373 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_DEVICE_TABLE(spi, ad5360_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static struct spi_driver ad5360_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .name = "ad5360",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .probe = ad5360_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .remove = ad5360_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .id_table = ad5360_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) module_spi_driver(ad5360_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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