^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * LTC2617, LTC2619, LTC2626, LTC2627, LTC2629, LTC2631, LTC2633, LTC2635
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Digital to analog converters driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD5064_MAX_DAC_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD5064_MAX_VREFS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD5064_ADDR(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD5064_CMD(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD5064_ADDR_ALL_DAC 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD5064_CMD_WRITE_INPUT_N 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD5064_CMD_UPDATE_DAC_N 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD5064_CMD_POWERDOWN_DAC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD5064_CMD_CLEAR 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD5064_CMD_LDAC_MASK 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD5064_CMD_RESET 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD5064_CMD_CONFIG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD5064_CMD_RESET_V2 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD5064_CMD_CONFIG_V2 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AD5064_LDAC_PWRDN_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AD5064_LDAC_PWRDN_1K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AD5064_LDAC_PWRDN_100K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD5064_LDAC_PWRDN_3STATE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * enum ad5064_regmap_type - Register layout variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @AD5064_REGMAP_ADI: Old Analog Devices register map layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @AD5064_REGMAP_ADI2: New Analog Devices register map layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @AD5064_REGMAP_LTC: LTC register map layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum ad5064_regmap_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) AD5064_REGMAP_ADI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * struct ad5064_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @shared_vref: whether the vref supply is shared between channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @internal_vref: internal reference voltage. 0 if the chip has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * internal vref.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @channels: channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @num_channels: number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @regmap_type: register map layout variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct ad5064_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool shared_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long internal_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum ad5064_regmap_type regmap_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ad5064_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int addr, unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * struct ad5064_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @dev: the device for this driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @chip_info: chip model specific constants, available modes etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @vref_reg: vref supply regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @pwr_down: whether channel is powered down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @pwr_down_mode: channel's current power down mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @dac_cache: current DAC raw value (chip does not support readback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @use_internal_vref: set to true if the internal reference voltage should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @write: register write callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @lock: maintain consistency between cached and dev state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @data: i2c/spi transfer buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ad5064_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct ad5064_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool pwr_down[AD5064_MAX_DAC_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool use_internal_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ad5064_write_func write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 i2c[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __be32 spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum ad5064_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ID_AD5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ID_AD5025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ID_AD5044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ID_AD5045,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ID_AD5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ID_AD5064_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ID_AD5065,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ID_AD5625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ID_AD5625R_1V25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ID_AD5625R_2V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ID_AD5627,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ID_AD5627R_1V25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ID_AD5627R_2V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ID_AD5628_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ID_AD5628_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ID_AD5629_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ID_AD5629_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ID_AD5645R_1V25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ID_AD5645R_2V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ID_AD5647R_1V25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ID_AD5647R_2V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ID_AD5648_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ID_AD5648_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ID_AD5665,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ID_AD5665R_1V25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ID_AD5665R_2V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ID_AD5666_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ID_AD5666_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ID_AD5667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ID_AD5667R_1V25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ID_AD5667R_2V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ID_AD5668_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ID_AD5668_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ID_AD5669_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ID_AD5669_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ID_LTC2606,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ID_LTC2607,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ID_LTC2609,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ID_LTC2616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ID_LTC2617,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ID_LTC2619,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ID_LTC2626,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ID_LTC2627,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ID_LTC2629,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ID_LTC2631_L12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ID_LTC2631_H12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ID_LTC2631_L10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ID_LTC2631_H10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ID_LTC2631_L8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ID_LTC2631_H8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ID_LTC2633_L12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ID_LTC2633_H12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ID_LTC2633_L10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ID_LTC2633_H10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ID_LTC2633_L8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ID_LTC2633_H8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ID_LTC2635_L12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ID_LTC2635_H12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ID_LTC2635_L10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ID_LTC2635_H10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ID_LTC2635_L8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ID_LTC2635_H8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int addr, unsigned int val, unsigned int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return st->write(st, cmd, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int val, address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (st->chip_info->regmap_type == AD5064_REGMAP_LTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) address = chan->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (st->chip_info->regmap_type == AD5064_REGMAP_ADI2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) shift = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val = (0x1 << chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) address = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (st->pwr_down[chan->channel])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val |= st->pwr_down_mode[chan->channel] << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, address, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const ad5064_powerdown_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "1kohm_to_gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "100kohm_to_gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "three_state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char * const ltc2617_powerdown_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "90kohm_to_gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return st->pwr_down_mode[chan->channel] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const struct iio_chan_spec *chan, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) st->pwr_down_mode[chan->channel] = mode + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = ad5064_sync_powerdown_mode(st, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct iio_enum ad5064_powerdown_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .items = ad5064_powerdown_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_items = ARRAY_SIZE(ad5064_powerdown_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .get = ad5064_get_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .set = ad5064_set_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct iio_enum ltc2617_powerdown_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .items = ltc2617_powerdown_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_items = ARRAY_SIZE(ltc2617_powerdown_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .get = ad5064_get_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .set = ad5064_set_powerdown_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uintptr_t private, const struct iio_chan_spec *chan, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) bool pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = strtobool(buf, &pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) st->pwr_down[chan->channel] = pwr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = ad5064_sync_powerdown_mode(st, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int ad5064_get_vref(struct ad5064_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct iio_chan_spec const *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (st->use_internal_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return st->chip_info->internal_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) i = st->chip_info->shared_vref ? 0 : chan->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return regulator_get_voltage(st->vref_reg[i].consumer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int ad5064_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *val = st->dac_cache[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) scale_uv = ad5064_get_vref(st, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (scale_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *val = scale_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int ad5064_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (val >= (1 << chan->scan_type.realbits) || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) chan->address, val, chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) st->dac_cache[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct iio_info ad5064_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .read_raw = ad5064_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .write_raw = ad5064_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .read = ad5064_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .write = ad5064_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5064_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct iio_chan_spec_ext_info ltc2617_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .name = "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .read = ad5064_read_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .write = ad5064_write_dac_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) IIO_ENUM("powerdown_mode", IIO_SEPARATE, <c2617_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) IIO_ENUM_AVAILABLE("powerdown_mode", <c2617_powerdown_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define AD5064_CHANNEL(chan, addr, bits, _shift, _ext_info) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .channel = (chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .address = addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .realbits = (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ext_info = (_ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DECLARE_AD5064_CHANNELS(name, bits, shift, ext_info) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const struct iio_chan_spec name[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) AD5064_CHANNEL(1, 1, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) AD5064_CHANNEL(2, 2, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) AD5064_CHANNEL(3, 3, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) AD5064_CHANNEL(4, 4, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) AD5064_CHANNEL(5, 5, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) AD5064_CHANNEL(6, 6, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) AD5064_CHANNEL(7, 7, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DECLARE_AD5065_CHANNELS(name, bits, shift, ext_info) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct iio_chan_spec name[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) AD5064_CHANNEL(1, 3, bits, shift, ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static DECLARE_AD5064_CHANNELS(ad5024_channels, 12, 8, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static DECLARE_AD5064_CHANNELS(ad5044_channels, 14, 6, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static DECLARE_AD5064_CHANNELS(ad5064_channels, 16, 4, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static DECLARE_AD5065_CHANNELS(ad5025_channels, 12, 8, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static DECLARE_AD5065_CHANNELS(ad5045_channels, 14, 6, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static DECLARE_AD5065_CHANNELS(ad5065_channels, 16, 4, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static DECLARE_AD5064_CHANNELS(ad5629_channels, 12, 4, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static DECLARE_AD5064_CHANNELS(ad5645_channels, 14, 2, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0, ad5064_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static DECLARE_AD5064_CHANNELS(ltc2607_channels, 16, 0, ltc2617_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static DECLARE_AD5064_CHANNELS(ltc2617_channels, 14, 2, ltc2617_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static DECLARE_AD5064_CHANNELS(ltc2627_channels, 12, 4, ltc2617_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define ltc2631_12_channels ltc2627_channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static DECLARE_AD5064_CHANNELS(ltc2631_10_channels, 10, 6, ltc2617_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static DECLARE_AD5064_CHANNELS(ltc2631_8_channels, 8, 8, ltc2617_ext_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define LTC2631_INFO(vref, pchannels, nchannels) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .shared_vref = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .internal_vref = vref, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .channels = pchannels, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .num_channels = nchannels, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .regmap_type = AD5064_REGMAP_LTC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [ID_AD5024] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .channels = ad5024_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [ID_AD5025] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .channels = ad5025_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [ID_AD5044] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .channels = ad5044_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [ID_AD5045] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .channels = ad5045_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [ID_AD5064] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .channels = ad5064_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [ID_AD5064_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .channels = ad5064_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [ID_AD5065] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .channels = ad5065_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [ID_AD5625] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [ID_AD5625R_1V25] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .internal_vref = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [ID_AD5625R_2V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [ID_AD5627] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [ID_AD5627R_1V25] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .internal_vref = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [ID_AD5627R_2V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [ID_AD5628_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .channels = ad5024_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [ID_AD5628_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .internal_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .channels = ad5024_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [ID_AD5629_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [ID_AD5629_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .internal_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .channels = ad5629_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) [ID_AD5645R_1V25] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .internal_vref = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .channels = ad5645_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [ID_AD5645R_2V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .channels = ad5645_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [ID_AD5647R_1V25] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .internal_vref = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .channels = ad5645_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) [ID_AD5647R_2V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .channels = ad5645_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) [ID_AD5648_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .channels = ad5044_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) [ID_AD5648_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .internal_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .channels = ad5044_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [ID_AD5665] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) [ID_AD5665R_1V25] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .internal_vref = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) [ID_AD5665R_2V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [ID_AD5666_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .channels = ad5064_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [ID_AD5666_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .internal_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .channels = ad5064_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [ID_AD5667] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [ID_AD5667R_1V25] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .internal_vref = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [ID_AD5667R_2V5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .regmap_type = AD5064_REGMAP_ADI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [ID_AD5668_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .channels = ad5064_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [ID_AD5668_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .internal_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .channels = ad5064_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [ID_AD5669_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .internal_vref = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [ID_AD5669_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .internal_vref = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .channels = ad5669_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .regmap_type = AD5064_REGMAP_ADI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [ID_LTC2606] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .channels = ltc2607_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [ID_LTC2607] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .channels = ltc2607_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [ID_LTC2609] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .channels = ltc2607_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [ID_LTC2616] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .channels = ltc2617_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [ID_LTC2617] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .channels = ltc2617_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [ID_LTC2619] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .channels = ltc2617_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [ID_LTC2626] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .channels = ltc2627_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [ID_LTC2627] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .shared_vref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .channels = ltc2627_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [ID_LTC2629] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .shared_vref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .internal_vref = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .channels = ltc2627_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .regmap_type = AD5064_REGMAP_LTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [ID_LTC2631_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [ID_LTC2631_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [ID_LTC2631_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [ID_LTC2631_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [ID_LTC2631_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [ID_LTC2631_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [ID_LTC2633_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [ID_LTC2633_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [ID_LTC2633_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [ID_LTC2633_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [ID_LTC2633_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [ID_LTC2633_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [ID_LTC2635_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [ID_LTC2635_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [ID_LTC2635_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [ID_LTC2635_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [ID_LTC2635_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [ID_LTC2635_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const char * const ad5064_vref_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "vrefA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "vrefB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "vrefC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "vrefD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const char *ad5064_vref_name(struct ad5064_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) unsigned int vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int ad5064_set_config(struct ad5064_state *st, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) switch (st->chip_info->regmap_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case AD5064_REGMAP_ADI2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) cmd = AD5064_CMD_CONFIG_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) cmd = AD5064_CMD_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ad5064_write(st, cmd, 0, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int ad5064_request_vref(struct ad5064_state *st, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) for (i = 0; i < ad5064_num_vref(st); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) st->vref_reg[i].supply = ad5064_vref_name(st, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!st->chip_info->internal_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return devm_regulator_bulk_get(dev, ad5064_num_vref(st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * This assumes that when the regulator has an internal VREF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * there is only one external VREF connection, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * currently the case for all supported devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) st->vref_reg[0].consumer = devm_regulator_get_optional(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!IS_ERR(st->vref_reg[0].consumer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = PTR_ERR(st->vref_reg[0].consumer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* If no external regulator was supplied use the internal VREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) st->use_internal_vref = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = ad5064_set_config(st, AD5064_CONFIG_INT_VREF_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_err(dev, "Failed to enable internal vref: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int ad5064_probe(struct device *dev, enum ad5064_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) const char *name, ad5064_write_func write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct ad5064_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) unsigned int midscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_set_drvdata(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) st->chip_info = &ad5064_chip_info_tbl[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) st->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) st->write = write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = ad5064_request_vref(st, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!st->use_internal_vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) indio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) indio_dev->info = &ad5064_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) midscale = (1 << indio_dev->channels[0].scan_type.realbits) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) for (i = 0; i < st->chip_info->num_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) st->dac_cache[i] = midscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!st->use_internal_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int ad5064_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct ad5064_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!st->use_internal_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #if IS_ENABLED(CONFIG_SPI_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int addr, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct spi_device *spi = to_spi_device(st->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return spi_write(spi, &st->data.spi, sizeof(st->data.spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static int ad5064_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return ad5064_probe(&spi->dev, id->driver_data, id->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ad5064_spi_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int ad5064_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ad5064_remove(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const struct spi_device_id ad5064_spi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {"ad5024", ID_AD5024},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {"ad5025", ID_AD5025},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {"ad5044", ID_AD5044},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {"ad5045", ID_AD5045},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {"ad5064", ID_AD5064},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {"ad5064-1", ID_AD5064_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {"ad5065", ID_AD5065},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {"ad5628-1", ID_AD5628_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {"ad5628-2", ID_AD5628_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {"ad5648-1", ID_AD5648_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {"ad5648-2", ID_AD5648_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {"ad5666-1", ID_AD5666_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {"ad5666-2", ID_AD5666_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {"ad5668-1", ID_AD5668_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {"ad5668-2", ID_AD5668_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) MODULE_DEVICE_TABLE(spi, ad5064_spi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static struct spi_driver ad5064_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = "ad5064",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .probe = ad5064_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .remove = ad5064_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .id_table = ad5064_spi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int __init ad5064_spi_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return spi_register_driver(&ad5064_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static void ad5064_spi_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) spi_unregister_driver(&ad5064_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static inline int ad5064_spi_register_driver(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static inline void ad5064_spi_unregister_driver(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #if IS_ENABLED(CONFIG_I2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned int addr, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct i2c_client *i2c = to_i2c_client(st->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int cmd_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) switch (st->chip_info->regmap_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case AD5064_REGMAP_ADI2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) cmd_shift = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) cmd_shift = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) st->data.i2c[0] = (cmd << cmd_shift) | addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) put_unaligned_be16(val, &st->data.i2c[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret = i2c_master_send(i2c, st->data.i2c, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int ad5064_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return ad5064_probe(&i2c->dev, id->driver_data, id->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ad5064_i2c_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static int ad5064_i2c_remove(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return ad5064_remove(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const struct i2c_device_id ad5064_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {"ad5625", ID_AD5625 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {"ad5625r-1v25", ID_AD5625R_1V25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {"ad5625r-2v5", ID_AD5625R_2V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {"ad5627", ID_AD5627 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {"ad5627r-1v25", ID_AD5627R_1V25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {"ad5627r-2v5", ID_AD5627R_2V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {"ad5629-1", ID_AD5629_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {"ad5629-2", ID_AD5629_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {"ad5629-3", ID_AD5629_2}, /* similar enough to ad5629-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {"ad5645r-1v25", ID_AD5645R_1V25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {"ad5645r-2v5", ID_AD5645R_2V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {"ad5665", ID_AD5665 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {"ad5665r-1v25", ID_AD5665R_1V25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {"ad5665r-2v5", ID_AD5665R_2V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {"ad5667", ID_AD5667 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {"ad5667r-1v25", ID_AD5667R_1V25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {"ad5667r-2v5", ID_AD5667R_2V5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {"ad5669-1", ID_AD5669_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {"ad5669-2", ID_AD5669_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {"ad5669-3", ID_AD5669_2}, /* similar enough to ad5669-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {"ltc2606", ID_LTC2606},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {"ltc2607", ID_LTC2607},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {"ltc2609", ID_LTC2609},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {"ltc2616", ID_LTC2616},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {"ltc2617", ID_LTC2617},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {"ltc2619", ID_LTC2619},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {"ltc2626", ID_LTC2626},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {"ltc2627", ID_LTC2627},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {"ltc2629", ID_LTC2629},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {"ltc2631-l12", ID_LTC2631_L12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {"ltc2631-h12", ID_LTC2631_H12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {"ltc2631-l10", ID_LTC2631_L10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {"ltc2631-h10", ID_LTC2631_H10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {"ltc2631-l8", ID_LTC2631_L8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {"ltc2631-h8", ID_LTC2631_H8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {"ltc2633-l12", ID_LTC2633_L12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {"ltc2633-h12", ID_LTC2633_H12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {"ltc2633-l10", ID_LTC2633_L10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {"ltc2633-h10", ID_LTC2633_H10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {"ltc2633-l8", ID_LTC2633_L8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {"ltc2633-h8", ID_LTC2633_H8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {"ltc2635-l12", ID_LTC2635_L12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {"ltc2635-h12", ID_LTC2635_H12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {"ltc2635-l10", ID_LTC2635_L10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {"ltc2635-h10", ID_LTC2635_H10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {"ltc2635-l8", ID_LTC2635_L8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {"ltc2635-h8", ID_LTC2635_H8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static struct i2c_driver ad5064_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .name = "ad5064",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .probe = ad5064_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .remove = ad5064_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .id_table = ad5064_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int __init ad5064_i2c_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return i2c_add_driver(&ad5064_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static void __exit ad5064_i2c_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) i2c_del_driver(&ad5064_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static inline int ad5064_i2c_register_driver(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static inline void ad5064_i2c_unregister_driver(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int __init ad5064_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = ad5064_spi_register_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ret = ad5064_i2c_register_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ad5064_spi_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) module_init(ad5064_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static void __exit ad5064_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ad5064_i2c_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ad5064_spi_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) module_exit(ad5064_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags