^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014-2015 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/buffer_impl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/buffer-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/buffer-dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The IIO DMAengine buffer combines the generic IIO DMA buffer infrastructure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * with the DMAengine framework. The generic IIO DMA buffer infrastructure is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * used to manage the buffer memory and implement the IIO buffer operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * while the DMAengine framework is used to perform the DMA transfers. Combined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * this results in a device independent fully functional DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * implementation that can be used by device drivers for peripherals which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * connected to a DMA controller which has a DMAengine driver implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct dmaengine_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct iio_dma_buffer_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) size_t align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) size_t max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct dmaengine_buffer *iio_buffer_to_dmaengine_buffer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct iio_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return container_of(buffer, struct dmaengine_buffer, queue.buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void iio_dmaengine_buffer_block_done(void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct dmaengine_result *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct iio_dma_buffer_block *block = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spin_lock_irqsave(&block->queue->list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) list_del(&block->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) spin_unlock_irqrestore(&block->queue->list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) block->bytes_used -= result->residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) iio_dma_buffer_block_done(block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct iio_dma_buffer_block *block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct dmaengine_buffer *dmaengine_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) iio_buffer_to_dmaengine_buffer(&queue->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) block->bytes_used = min(block->size, dmaengine_buffer->max_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) block->bytes_used = rounddown(block->bytes_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dmaengine_buffer->align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) desc = dmaengine_prep_slave_single(dmaengine_buffer->chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) block->phys_addr, block->bytes_used, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) desc->callback_result = iio_dmaengine_buffer_block_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) desc->callback_param = block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (dma_submit_error(cookie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spin_lock_irq(&dmaengine_buffer->queue.list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) list_add_tail(&block->head, &dmaengine_buffer->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) spin_unlock_irq(&dmaengine_buffer->queue.list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dma_async_issue_pending(dmaengine_buffer->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void iio_dmaengine_buffer_abort(struct iio_dma_buffer_queue *queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct dmaengine_buffer *dmaengine_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) iio_buffer_to_dmaengine_buffer(&queue->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dmaengine_terminate_sync(dmaengine_buffer->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) iio_dma_buffer_block_list_abort(queue, &dmaengine_buffer->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void iio_dmaengine_buffer_release(struct iio_buffer *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct dmaengine_buffer *dmaengine_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) iio_buffer_to_dmaengine_buffer(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) iio_dma_buffer_release(&dmaengine_buffer->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) kfree(dmaengine_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .read = iio_dma_buffer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .set_bytes_per_datum = iio_dma_buffer_set_bytes_per_datum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .set_length = iio_dma_buffer_set_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .request_update = iio_dma_buffer_request_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .enable = iio_dma_buffer_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .disable = iio_dma_buffer_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .data_available = iio_dma_buffer_data_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .release = iio_dmaengine_buffer_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .modes = INDIO_BUFFER_HARDWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .flags = INDIO_BUFFER_FLAG_FIXED_WATERMARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct iio_dma_buffer_ops iio_dmaengine_default_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .submit = iio_dmaengine_buffer_submit_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .abort = iio_dmaengine_buffer_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static ssize_t iio_dmaengine_buffer_get_length_align(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dmaengine_buffer *dmaengine_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) iio_buffer_to_dmaengine_buffer(indio_dev->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return sprintf(buf, "%zu\n", dmaengine_buffer->align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static IIO_DEVICE_ATTR(length_align_bytes, 0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) iio_dmaengine_buffer_get_length_align, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct attribute *iio_dmaengine_buffer_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &iio_dev_attr_length_align_bytes.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * iio_dmaengine_buffer_alloc() - Allocate new buffer which uses DMAengine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @dev: Parent device for the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @channel: DMA channel name, typically "rx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * This allocates a new IIO buffer which internally uses the DMAengine framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * to perform its transfers. The parent device will be used to request the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Once done using the buffer iio_dmaengine_buffer_free() should be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * release it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const char *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct dmaengine_buffer *dmaengine_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int width, src_width, dest_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct dma_slave_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dmaengine_buffer = kzalloc(sizeof(*dmaengine_buffer), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!dmaengine_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chan = dma_request_chan(dev, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = PTR_ERR(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = dma_get_slave_caps(chan, &caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Needs to be aligned to the maximum of the minimums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (caps.src_addr_widths)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) src_width = __ffs(caps.src_addr_widths);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) src_width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (caps.dst_addr_widths)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dest_width = __ffs(caps.dst_addr_widths);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dest_width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) width = max(src_width, dest_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) INIT_LIST_HEAD(&dmaengine_buffer->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dmaengine_buffer->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dmaengine_buffer->align = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dmaengine_buffer->max_size = dma_get_max_seg_size(chan->device->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) iio_dma_buffer_init(&dmaengine_buffer->queue, chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) &iio_dmaengine_default_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) iio_buffer_set_attrs(&dmaengine_buffer->queue.buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) iio_dmaengine_buffer_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dmaengine_buffer->queue.buffer.access = &iio_dmaengine_buffer_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return &dmaengine_buffer->queue.buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) kfree(dmaengine_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * iio_dmaengine_buffer_free() - Free dmaengine buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @buffer: Buffer to free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Frees a buffer previously allocated with iio_dmaengine_buffer_alloc().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void iio_dmaengine_buffer_free(struct iio_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct dmaengine_buffer *dmaengine_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) iio_buffer_to_dmaengine_buffer(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) iio_dma_buffer_exit(&dmaengine_buffer->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dma_release_channel(dmaengine_buffer->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) iio_buffer_put(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void __devm_iio_dmaengine_buffer_free(struct device *dev, void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) iio_dmaengine_buffer_free(*(struct iio_buffer **)res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * devm_iio_dmaengine_buffer_alloc() - Resource-managed iio_dmaengine_buffer_alloc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @dev: Parent device for the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @channel: DMA channel name, typically "rx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * This allocates a new IIO buffer which internally uses the DMAengine framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * to perform its transfers. The parent device will be used to request the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * The buffer will be automatically de-allocated once the device gets destroyed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct iio_buffer *devm_iio_dmaengine_buffer_alloc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const char *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct iio_buffer **bufferp, *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bufferp = devres_alloc(__devm_iio_dmaengine_buffer_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) sizeof(*bufferp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!bufferp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) buffer = iio_dmaengine_buffer_alloc(dev, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (IS_ERR(buffer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) devres_free(bufferp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *bufferp = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) devres_add(dev, bufferp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) EXPORT_SYMBOL_GPL(devm_iio_dmaengine_buffer_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DESCRIPTION("DMA buffer for the IIO framework");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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