^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx XADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __IIO_XILINX_XADC__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __IIO_XILINX_XADC__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct iio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct xadc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int xadc_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum iio_event_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int xadc_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum iio_event_direction dir, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int xadc_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int *val, int *val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int xadc_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int val, int val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum xadc_external_mux_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) XADC_EXTERNAL_MUX_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) XADC_EXTERNAL_MUX_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) XADC_EXTERNAL_MUX_DUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct xadc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct xadc_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) uint16_t threshold[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint16_t temp_hysteresis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int alarm_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) uint16_t *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct iio_trigger *trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct iio_trigger *convst_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct iio_trigger *samplerate_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum xadc_external_mux_mode external_mux_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int zynq_masked_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int zynq_intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct delayed_work zynq_unmask_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct xadc_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long (*get_dclk_rate)(struct xadc *xadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) irqreturn_t (*interrupt_handler)(int irq, void *devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint16_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) lockdep_assert_held(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return xadc->ops->read(xadc, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint16_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) lockdep_assert_held(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return xadc->ops->write(xadc, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint16_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mutex_lock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = _xadc_read_adc_reg(xadc, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mutex_unlock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint16_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mutex_lock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = _xadc_write_adc_reg(xadc, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mutex_unlock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* XADC hardmacro register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define XADC_REG_TEMP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XADC_REG_VCCINT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XADC_REG_VCCAUX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XADC_REG_VPVN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XADC_REG_VREFP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XADC_REG_VREFN 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define XADC_REG_VCCBRAM 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define XADC_REG_VCCPINT 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define XADC_REG_VCCPAUX 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define XADC_REG_VCCO_DDR 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XADC_REG_VAUX(x) (0x10 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define XADC_REG_MAX_TEMP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XADC_REG_MAX_VCCINT 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define XADC_REG_MAX_VCCAUX 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define XADC_REG_MAX_VCCBRAM 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define XADC_REG_MIN_TEMP 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define XADC_REG_MIN_VCCINT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define XADC_REG_MIN_VCCAUX 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XADC_REG_MIN_VCCBRAM 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define XADC_REG_MAX_VCCPINT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XADC_REG_MAX_VCCPAUX 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XADC_REG_MAX_VCCO_DDR 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define XADC_REG_MIN_VCCPINT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define XADC_REG_MIN_VCCPAUX 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define XADC_REG_MIN_VCCO_DDR 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define XADC_REG_CONF0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define XADC_REG_CONF1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define XADC_REG_CONF2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define XADC_REG_SEQ(x) (0x48 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define XADC_REG_INPUT_MODE(x) (0x4c + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define XADC_REG_THRESHOLD(x) (0x50 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define XADC_REG_FLAG 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define XADC_CONF0_EC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define XADC_CONF0_ACQ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define XADC_CONF0_MUX BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define XADC_CONF0_CHAN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define XADC_CONF1_SEQ_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define XADC_CONF1_SEQ_DEFAULT (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define XADC_CONF1_SEQ_CONTINUOUS (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define XADC_CONF1_SEQ_INDEPENDENT (8 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define XADC_CONF1_ALARM_MASK 0x0f0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define XADC_CONF2_DIV_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define XADC_CONF2_DIV_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define XADC_CONF2_PD_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define XADC_CONF2_PD_NONE (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define XADC_CONF2_PD_ADC_B (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define XADC_CONF2_PD_BOTH (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define XADC_ALARM_TEMP_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define XADC_ALARM_VCCINT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define XADC_ALARM_VCCAUX_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define XADC_ALARM_OT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define XADC_ALARM_VCCBRAM_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define XADC_ALARM_VCCPINT_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define XADC_ALARM_VCCPAUX_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define XADC_ALARM_VCCODDR_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define XADC_THRESHOLD_TEMP_MAX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XADC_THRESHOLD_VCCINT_MAX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define XADC_THRESHOLD_VCCAUX_MAX 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define XADC_THRESHOLD_OT_MAX 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XADC_THRESHOLD_TEMP_MIN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XADC_THRESHOLD_VCCINT_MIN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define XADC_THRESHOLD_VCCAUX_MIN 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XADC_THRESHOLD_OT_MIN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define XADC_THRESHOLD_VCCBRAM_MAX 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define XADC_THRESHOLD_VCCPINT_MAX 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define XADC_THRESHOLD_VCCPAUX_MAX 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define XADC_THRESHOLD_VCCODDR_MAX 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define XADC_THRESHOLD_VCCBRAM_MIN 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define XADC_THRESHOLD_VCCPINT_MIN 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define XADC_THRESHOLD_VCCPAUX_MIN 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define XADC_THRESHOLD_VCCODDR_MIN 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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