^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx XADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "xilinx-xadc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct iio_chan_spec *xadc_event_to_channel(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct iio_dev *indio_dev, unsigned int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) case XADC_THRESHOLD_OT_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) case XADC_THRESHOLD_TEMP_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return &indio_dev->channels[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) case XADC_THRESHOLD_VCCINT_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) case XADC_THRESHOLD_VCCAUX_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return &indio_dev->channels[event];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return &indio_dev->channels[event-1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Temperature threshold error, we don't handle this yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (event == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) chan = xadc_event_to_channel(indio_dev, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The temperature channel only supports over-temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * For other channels we don't know whether it is a upper or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * lower threshold event. Userspace will have to check the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * channel value if it wants to know.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for_each_set_bit(i, &events, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) xadc_handle_event(indio_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static unsigned int xadc_get_threshold_offset(const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) offset = XADC_THRESHOLD_OT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (chan->channel < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) offset = chan->channel + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) offset = chan->channel + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (dir == IIO_EV_DIR_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static unsigned int xadc_get_alarm_mask(const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (chan->type == IIO_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return XADC_ALARM_OT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (chan->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return XADC_ALARM_VCCINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return XADC_ALARM_VCCAUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return XADC_ALARM_VCCBRAM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return XADC_ALARM_VCCPINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return XADC_ALARM_VCCPAUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return XADC_ALARM_VCCODDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* We will never get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int xadc_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct xadc *xadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return (bool)(xadc->alarm_mask & xadc_get_alarm_mask(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int xadc_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int alarm = xadc_get_alarm_mask(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct xadc *xadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint16_t cfg, old_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mutex_lock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) xadc->alarm_mask |= alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) xadc->alarm_mask &= ~alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) xadc->ops->update_alarm(xadc, xadc->alarm_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = _xadc_read_adc_reg(xadc, XADC_REG_CONF1, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) old_cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cfg |= XADC_CONF1_ALARM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cfg &= ~((xadc->alarm_mask & 0xf0) << 4); /* bram, pint, paux, ddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cfg &= ~((xadc->alarm_mask & 0x08) >> 3); /* ot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cfg &= ~((xadc->alarm_mask & 0x07) << 1); /* temp, vccint, vccaux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (old_cfg != cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = _xadc_write_adc_reg(xadc, XADC_REG_CONF1, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mutex_unlock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Register value is msb aligned, the lower 4 bits are ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define XADC_THRESHOLD_VALUE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int xadc_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int offset = xadc_get_threshold_offset(chan, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct xadc *xadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *val = xadc->threshold[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case IIO_EV_INFO_HYSTERESIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *val = xadc->temp_hysteresis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *val >>= XADC_THRESHOLD_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int xadc_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int offset = xadc_get_threshold_offset(chan, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct xadc *xadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val <<= XADC_THRESHOLD_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (val < 0 || val > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mutex_lock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) xadc->threshold[offset] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case IIO_EV_INFO_HYSTERESIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) xadc->temp_hysteresis = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mutex_unlock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * According to the datasheet we need to set the lower 4 bits to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 0x3, otherwise 125 degree celsius will be used as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Since we store the hysteresis as relative (to the threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * value, but the hardware expects an absolute value we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * recalcualte this value whenever the hysteresis or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * threshold changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (xadc->threshold[offset] < xadc->temp_hysteresis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) xadc->threshold[offset + 4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) xadc->threshold[offset + 4] = xadc->threshold[offset] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) xadc->temp_hysteresis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset + 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) xadc->threshold[offset + 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (info == IIO_EV_INFO_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mutex_unlock(&xadc->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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