^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale Vybrid vf610 ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* This will be the driver name the kernel reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_NAME "vf610-adc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Vybrid/IMX ADC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VF610_REG_ADC_HC0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VF610_REG_ADC_HC1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VF610_REG_ADC_HS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VF610_REG_ADC_R0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VF610_REG_ADC_R1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VF610_REG_ADC_CFG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VF610_REG_ADC_GC 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VF610_REG_ADC_GS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VF610_REG_ADC_CV 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VF610_REG_ADC_OFS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VF610_REG_ADC_CAL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VF610_REG_ADC_PCTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Configuration register field define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VF610_ADC_MODE_BIT8 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VF610_ADC_MODE_BIT10 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VF610_ADC_MODE_BIT12 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VF610_ADC_MODE_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VF610_ADC_BUSCLK2_SEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VF610_ADC_ALTCLK_SEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VF610_ADC_ADACK_SEL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VF610_ADC_ADCCLK_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VF610_ADC_CLK_DIV2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VF610_ADC_CLK_DIV4 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VF610_ADC_CLK_DIV8 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VF610_ADC_CLK_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VF610_ADC_ADLSMP_LONG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VF610_ADC_ADSTS_SHORT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VF610_ADC_ADSTS_NORMAL 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VF610_ADC_ADSTS_LONG 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VF610_ADC_ADSTS_MASK 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VF610_ADC_ADLPC_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VF610_ADC_ADHSC_EN 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VF610_ADC_REFSEL_VALT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VF610_ADC_REFSEL_VBG 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VF610_ADC_ADTRG_HARD 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VF610_ADC_AVGS_8 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VF610_ADC_AVGS_16 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VF610_ADC_AVGS_32 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VF610_ADC_AVGS_MASK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VF610_ADC_OVWREN 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* General control register field define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VF610_ADC_ADACKEN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VF610_ADC_DMAEN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VF610_ADC_ACREN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VF610_ADC_ACFGT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VF610_ADC_ACFE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VF610_ADC_AVGEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VF610_ADC_ADCON 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VF610_ADC_CAL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Other field define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VF610_ADC_AIEN (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VF610_ADC_CONV_DISABLE 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VF610_ADC_HS_COCO0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VF610_ADC_CALF 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEFAULT_SAMPLE_TIME 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* V at 25°C of 696 mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VF610_VTEMP25_3V0 950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* V at 25°C of 699 mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VF610_VTEMP25_3V3 867
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Typical sensor slope coefficient at all temperatures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VF610_TEMP_SLOPE_COEFF 1840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum clk_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) VF610_ADCIOC_BUSCLK_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) VF610_ADCIOC_ALTCLK_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) VF610_ADCIOC_ADACK_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum vol_ref {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) VF610_ADCIOC_VR_VREF_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) VF610_ADCIOC_VR_VALT_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) VF610_ADCIOC_VR_VBG_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum average_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) VF610_ADC_SAMPLE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) VF610_ADC_SAMPLE_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) VF610_ADC_SAMPLE_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) VF610_ADC_SAMPLE_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) VF610_ADC_SAMPLE_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum conversion_mode_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) VF610_ADC_CONV_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) VF610_ADC_CONV_HIGH_SPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) VF610_ADC_CONV_LOW_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum lst_adder_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) VF610_ADCK_CYCLES_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) VF610_ADCK_CYCLES_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) VF610_ADCK_CYCLES_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) VF610_ADCK_CYCLES_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) VF610_ADCK_CYCLES_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) VF610_ADCK_CYCLES_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) VF610_ADCK_CYCLES_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) VF610_ADCK_CYCLES_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct vf610_adc_feature {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum clk_sel clk_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum vol_ref vol_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum conversion_mode_sel conv_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int res_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 lst_adder_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 default_sample_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool calibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool ovwren;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct vf610_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 max_adck_rate[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct vf610_adc_feature adc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 sample_freq_avail[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Ensure the timestamp is naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) s64 timestamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct vf610_adc_feature *adc_feature = &info->adc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 adck_period, lst_addr_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int divisor, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) adck_rate = info->max_adck_rate[adc_feature->conv_mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (adck_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* calculate clk divider which is within specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) divisor = ipg_rate / adck_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) adc_feature->clk_div = 1 << fls(divisor + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* fall-back value using a safe divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) adc_feature->clk_div = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) adck_rate = ipg_rate / adc_feature->clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Determine the long sample time adder value to be used based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * on the default minimum sample time provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) adck_period = NSEC_PER_SEC / adck_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lst_addr_min = adc_feature->default_sample_time / adck_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (vf610_lst_adder[i] > lst_addr_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) adc_feature->lst_adder_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Calculate ADC sample frequencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * which is the same as bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * SFCAdder: fixed to 6 ADCK cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) info->sample_freq_avail[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) adck_rate / (6 + vf610_hw_avgs[i] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline void vf610_adc_cfg_init(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct vf610_adc_feature *adc_feature = &info->adc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* set default Configuration for ADC controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) adc_feature->calibration = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) adc_feature->ovwren = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) adc_feature->res_mode = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) adc_feature->sample_rate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) vf610_adc_calculate_rates(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void vf610_adc_cfg_post_set(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct vf610_adc_feature *adc_feature = &info->adc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int cfg_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int gc_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) switch (adc_feature->clk_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case VF610_ADCIOC_ALTCLK_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cfg_data |= VF610_ADC_ALTCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case VF610_ADCIOC_ADACK_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cfg_data |= VF610_ADC_ADACK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* low power set for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cfg_data |= VF610_ADC_ADLPC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* enable high speed for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cfg_data |= VF610_ADC_ADHSC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* voltage reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (adc_feature->vol_ref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case VF610_ADCIOC_VR_VREF_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case VF610_ADCIOC_VR_VALT_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cfg_data |= VF610_ADC_REFSEL_VALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case VF610_ADCIOC_VR_VBG_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cfg_data |= VF610_ADC_REFSEL_VBG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(info->dev, "error voltage reference\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* data overwrite enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (adc_feature->ovwren)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cfg_data |= VF610_ADC_OVWREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel(gc_data, info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void vf610_adc_calibration(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int adc_gc, hc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!info->adc_feature.calibration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* enable calibration interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) adc_gc = readl(info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(info->dev, "Timeout for adc calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) adc_gc = readl(info->regs + VF610_REG_ADC_GS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (adc_gc & VF610_ADC_CALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(info->dev, "ADC calibration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) info->adc_feature.calibration = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void vf610_adc_cfg_set(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct vf610_adc_feature *adc_feature = &(info->adc_feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cfg_data &= ~VF610_ADC_ADLPC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cfg_data |= VF610_ADC_ADLPC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cfg_data &= ~VF610_ADC_ADHSC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cfg_data |= VF610_ADC_ADHSC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void vf610_adc_sample_set(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct vf610_adc_feature *adc_feature = &(info->adc_feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int cfg_data, gc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) gc_data = readl(info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* resolution mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cfg_data &= ~VF610_ADC_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (adc_feature->res_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cfg_data |= VF610_ADC_MODE_BIT8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cfg_data |= VF610_ADC_MODE_BIT10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cfg_data |= VF610_ADC_MODE_BIT12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(info->dev, "error resolution mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* clock select and clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) switch (adc_feature->clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cfg_data |= VF610_ADC_CLK_DIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cfg_data |= VF610_ADC_CLK_DIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cfg_data |= VF610_ADC_CLK_DIV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch (adc_feature->clk_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case VF610_ADCIOC_BUSCLK_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(info->dev, "error clk divider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * determined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) switch (adc_feature->lst_adder_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case VF610_ADCK_CYCLES_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case VF610_ADCK_CYCLES_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cfg_data |= VF610_ADC_ADSTS_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case VF610_ADCK_CYCLES_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cfg_data |= VF610_ADC_ADSTS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case VF610_ADCK_CYCLES_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cfg_data |= VF610_ADC_ADSTS_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case VF610_ADCK_CYCLES_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cfg_data |= VF610_ADC_ADLSMP_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case VF610_ADCK_CYCLES_17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cfg_data |= VF610_ADC_ADLSMP_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cfg_data |= VF610_ADC_ADSTS_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case VF610_ADCK_CYCLES_21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cfg_data |= VF610_ADC_ADLSMP_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cfg_data |= VF610_ADC_ADSTS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case VF610_ADCK_CYCLES_25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cfg_data |= VF610_ADC_ADLSMP_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cfg_data |= VF610_ADC_ADSTS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(info->dev, "error in sample time select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* update hardware average selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cfg_data &= ~VF610_ADC_AVGS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) gc_data &= ~VF610_ADC_AVGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) switch (adc_feature->sample_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case VF610_ADC_SAMPLE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case VF610_ADC_SAMPLE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gc_data |= VF610_ADC_AVGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case VF610_ADC_SAMPLE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) gc_data |= VF610_ADC_AVGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cfg_data |= VF610_ADC_AVGS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case VF610_ADC_SAMPLE_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) gc_data |= VF610_ADC_AVGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cfg_data |= VF610_ADC_AVGS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case VF610_ADC_SAMPLE_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gc_data |= VF610_ADC_AVGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) cfg_data |= VF610_ADC_AVGS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "error hardware sample average select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel(gc_data, info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void vf610_adc_hw_init(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* CFG: Feature set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) vf610_adc_cfg_post_set(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) vf610_adc_sample_set(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* adc calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) vf610_adc_calibration(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* CFG: power and speed set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) vf610_adc_cfg_set(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) info->adc_feature.conv_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) vf610_adc_calculate_rates(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) vf610_adc_hw_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return info->adc_feature.conv_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const char * const vf610_conv_modes[] = { "normal", "high-speed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "low-power" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct iio_enum vf610_conversion_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .items = vf610_conv_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .num_items = ARRAY_SIZE(vf610_conv_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .get = vf610_get_conversion_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .set = vf610_set_conversion_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define VF610_ADC_CHAN(_idx, _chan_type) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .type = (_chan_type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .channel = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .ext_info = vf610_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .scan_index = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .type = (_chan_type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .channel = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .scan_index = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct iio_chan_spec vf610_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) VF610_ADC_CHAN(0, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) VF610_ADC_CHAN(1, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) VF610_ADC_CHAN(2, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) VF610_ADC_CHAN(3, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) VF610_ADC_CHAN(4, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) VF610_ADC_CHAN(5, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) VF610_ADC_CHAN(6, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) VF610_ADC_CHAN(7, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) VF610_ADC_CHAN(8, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) VF610_ADC_CHAN(9, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) VF610_ADC_CHAN(10, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) VF610_ADC_CHAN(11, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) VF610_ADC_CHAN(12, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) VF610_ADC_CHAN(13, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) VF610_ADC_CHAN(14, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) VF610_ADC_CHAN(15, IIO_VOLTAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) IIO_CHAN_SOFT_TIMESTAMP(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int vf610_adc_read_data(struct vf610_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) result = readl(info->regs + VF610_REG_ADC_R0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) switch (info->adc_feature.res_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) result &= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) result &= 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) result &= 0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct iio_dev *indio_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int coco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) coco = readl(info->regs + VF610_REG_ADC_HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (coco & VF610_ADC_HS_COCO0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) info->value = vf610_adc_read_data(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (iio_buffer_enabled(indio_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) info->scan.chan = info->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) iio_push_to_buffers_with_timestamp(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &info->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static ssize_t vf610_show_samp_freq_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) len += scnprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "%u ", info->sample_freq_avail[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* replace trailing space by newline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct attribute *vf610_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct attribute_group vf610_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .attrs = vf610_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int vf610_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int hc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (iio_buffer_enabled(indio_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hc_cfg = VF610_ADC_ADCHC(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) hc_cfg |= VF610_ADC_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = wait_for_completion_interruptible_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) (&info->completion, VF610_ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *val = info->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Calculate in degree Celsius times 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Using the typical sensor slope of 1.84 mV/°C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 1000000 / VF610_TEMP_SLOPE_COEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *val = info->vref_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *val2 = info->adc_feature.res_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *val = info->sample_freq_avail[info->adc_feature.sample_rate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int vf610_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) i < ARRAY_SIZE(info->sample_freq_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (val == info->sample_freq_avail[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) info->adc_feature.sample_rate = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) vf610_adc_sample_set(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) val = readl(info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) val |= VF610_ADC_ADCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel(val, info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) channel = find_first_bit(indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) indio_dev->masklength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val = VF610_ADC_ADCHC(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) val |= VF610_ADC_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writel(val, info->regs + VF610_REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned int hc_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) val = readl(info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val &= ~VF610_ADC_ADCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) writel(val, info->regs + VF610_REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) hc_cfg |= VF610_ADC_CONV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) hc_cfg &= ~VF610_ADC_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .postenable = &vf610_adc_buffer_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .predisable = &vf610_adc_buffer_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .validate_scan_mask = &iio_validate_scan_mask_onehot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int vf610_adc_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned reg, unsigned writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if ((readval == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *readval = readl(info->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct iio_info vf610_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .read_raw = &vf610_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .write_raw = &vf610_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .debugfs_reg_access = &vf610_adc_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .attrs = &vf610_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const struct of_device_id vf610_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { .compatible = "fsl,vf610-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MODULE_DEVICE_TABLE(of, vf610_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int vf610_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct vf610_adc *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(&pdev->dev, "Failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) info->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (IS_ERR(info->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return PTR_ERR(info->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = devm_request_irq(info->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) vf610_adc_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_name(&pdev->dev), indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) info->clk = devm_clk_get(&pdev->dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PTR_ERR(info->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) info->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (IS_ERR(info->vref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return PTR_ERR(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = regulator_enable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) info->vref_uv = regulator_get_voltage(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) info->max_adck_rate, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &info->adc_feature.default_sample_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) init_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) indio_dev->info = &vf610_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) indio_dev->channels = vf610_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "Could not prepare or enable the clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) goto error_adc_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) vf610_adc_cfg_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) vf610_adc_hw_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) NULL, &iio_triggered_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto error_iio_device_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(&pdev->dev, "Couldn't register the device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto error_adc_buffer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) error_adc_buffer_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) error_iio_device_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) error_adc_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int vf610_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int vf610_adc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int hc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* ADC controller enters to stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) hc_cfg |= VF610_ADC_CONV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int vf610_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct vf610_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = regulator_enable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) vf610_adc_hw_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static struct platform_driver vf610_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .probe = vf610_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .remove = vf610_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .of_match_table = vf610_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .pm = &vf610_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) module_platform_driver(vf610_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MODULE_DESCRIPTION("Freescale VF610 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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