^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI tlc4541 ADC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Phil Reid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Datasheets can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * https://www.ti.com/lit/gpn/tlc3541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * https://www.ti.com/lit/gpn/tlc4541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The tlc4541 requires 24 clock cycles to start a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Conversion then takes 2.94us to complete before data is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Data is returned MSB first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct tlc4541_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct spi_transfer scan_single_xfer[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct spi_message scan_single_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 2 bytes data + 6 bytes padding + 8 bytes timestamp when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * call iio_push_to_buffers_with_timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __be16 rx_buf[8] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct tlc4541_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum tlc4541_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) TLC3541,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) TLC4541,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TLC4541_V_CHAN(bits, bitshift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .realbits = (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .shift = (bitshift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DECLARE_TLC4541_CHANNELS(name, bits, bitshift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TLC4541_V_CHAN(bits, bitshift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IIO_CHAN_SOFT_TIMESTAMP(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static DECLARE_TLC4541_CHANNELS(tlc3541, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static DECLARE_TLC4541_CHANNELS(tlc4541, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct tlc4541_chip_info tlc4541_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [TLC3541] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .channels = tlc3541_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .num_channels = ARRAY_SIZE(tlc3541_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [TLC4541] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .channels = tlc4541_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .num_channels = ARRAY_SIZE(tlc4541_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static irqreturn_t tlc4541_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct tlc4541_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int tlc4541_get_range(struct tlc4541_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) vref = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (vref < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) vref /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int tlc4541_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct tlc4541_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *val = be16_to_cpu(st->rx_buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *val = *val >> chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *val &= GENMASK(chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = tlc4541_get_range(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct iio_info tlc4541_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .read_raw = &tlc4541_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int tlc4541_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct tlc4541_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const struct tlc4541_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int8_t device_init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) info = &tlc4541_chip_info[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) indio_dev->channels = info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) indio_dev->num_channels = info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) indio_dev->info = &tlc4541_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* perform reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spi_write(spi, &device_init, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Setup default message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) st->scan_single_xfer[0].rx_buf = &st->rx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) st->scan_single_xfer[0].len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) st->scan_single_xfer[1].delay.value = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) st->scan_single_xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) st->scan_single_xfer[2].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spi_message_init_with_transfers(&st->scan_single_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) st->scan_single_xfer, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) st->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) &tlc4541_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto error_cleanup_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) error_cleanup_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int tlc4541_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct tlc4541_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct of_device_id tlc4541_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .compatible = "ti,tlc3541", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .compatible = "ti,tlc4541", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_DEVICE_TABLE(of, tlc4541_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct spi_device_id tlc4541_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {"tlc3541", TLC3541},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {"tlc4541", TLC4541},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_DEVICE_TABLE(spi, tlc4541_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct spi_driver tlc4541_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "tlc4541",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .of_match_table = tlc4541_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .probe = tlc4541_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .remove = tlc4541_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .id_table = tlc4541_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) module_spi_driver(tlc4541_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_AUTHOR("Phil Reid <preid@electromag.com.au>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_DESCRIPTION("Texas Instruments TLC4541 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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