^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADS8344 16-bit 8-Channel ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Gregory CLEMENT <gregory.clement@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Datasheet: https://www.ti.com/lit/ds/symlink/ads8344.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ADS8344_START BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ADS8344_SINGLE_END BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADS8344_CHANNEL(channel) ((channel) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADS8344_CLOCK_INTERNAL 0x2 /* PD1 = 1 and PD0 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct ads8344 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Lock protecting access to adc->tx_buff and rx_buff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * especially from concurrent read on sysfs file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 tx_buf ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 rx_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADS8344_VOLTAGE_CHANNEL(chan, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .channel = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .address = addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADS8344_VOLTAGE_CHANNEL_DIFF(chan1, chan2, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .channel = (chan1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .channel2 = (chan2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .differential = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .address = addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct iio_chan_spec ads8344_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADS8344_VOLTAGE_CHANNEL(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADS8344_VOLTAGE_CHANNEL(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ADS8344_VOLTAGE_CHANNEL(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ADS8344_VOLTAGE_CHANNEL(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ADS8344_VOLTAGE_CHANNEL(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ADS8344_VOLTAGE_CHANNEL(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ADS8344_VOLTAGE_CHANNEL(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ADS8344_VOLTAGE_CHANNEL(7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ADS8344_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ADS8344_VOLTAGE_CHANNEL_DIFF(2, 3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ADS8344_VOLTAGE_CHANNEL_DIFF(4, 5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ADS8344_VOLTAGE_CHANNEL_DIFF(6, 7, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ADS8344_VOLTAGE_CHANNEL_DIFF(1, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ADS8344_VOLTAGE_CHANNEL_DIFF(3, 2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ADS8344_VOLTAGE_CHANNEL_DIFF(5, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ADS8344_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int ads8344_adc_conversion(struct ads8344 *adc, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct spi_device *spi = adc->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) adc->tx_buf = ADS8344_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) adc->tx_buf |= ADS8344_SINGLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) adc->tx_buf |= ADS8344_CHANNEL(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) adc->tx_buf |= ADS8344_CLOCK_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = spi_write(spi, &adc->tx_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) udelay(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int ads8344_read_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct iio_chan_spec const *channel, int *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int *shift, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ads8344 *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *value = ads8344_adc_conversion(adc, channel->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) channel->differential);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (*value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *value = regulator_get_voltage(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (*value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* convert regulator output voltage to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *value /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *shift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct iio_info ads8344_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .read_raw = ads8344_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int ads8344_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct ads8344 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) indio_dev->name = dev_name(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) indio_dev->info = &ads8344_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) indio_dev->channels = ads8344_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) indio_dev->num_channels = ARRAY_SIZE(ads8344_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) adc->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (IS_ERR(adc->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return PTR_ERR(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int ads8344_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ads8344 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct of_device_id ads8344_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .compatible = "ti,ads8344", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(of, ads8344_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct spi_driver ads8344_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "ads8344",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .of_match_table = ads8344_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .probe = ads8344_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .remove = ads8344_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) module_spi_driver(ads8344_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_DESCRIPTION("ADS8344 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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