^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Texas Instruments ADS7950 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on iio/ad7923.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2011 Analog Devices Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2012 CS Systemes d'Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * And also on hwmon/ads79xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Nishanth Menon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * In case of ACPI, we use the 5000 mV as default for the reference pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Device tree users encode that via the vref-supply regulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TI_ADS7950_VA_MV_ACPI_DEFAULT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TI_ADS7950_CR_GPIO BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TI_ADS7950_CR_MANUAL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TI_ADS7950_CR_WRITE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TI_ADS7950_CR_RANGE_5V BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TI_ADS7950_CR_GPIO_DATA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TI_ADS7950_MAX_CHAN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TI_ADS7950_NUM_GPIOS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* val = value, dec = left shift, bits = number of bits of the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TI_ADS7950_EXTRACT(val, dec, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (((val) >> (dec)) & ((1 << (bits)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TI_ADS7950_MAN_CMD(cmd) (TI_ADS7950_CR_MANUAL | (cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TI_ADS7950_GPIO_CMD(cmd) (TI_ADS7950_CR_GPIO | (cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Manual mode configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TI_ADS7950_MAN_CMD_SETTINGS(st) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* GPIO mode configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TI_ADS7950_GPIO_CMD_SETTINGS(st) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ti_ads7950_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct spi_transfer ring_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct spi_transfer scan_single_xfer[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct spi_message ring_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct spi_message scan_single_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Lock to protect the spi xfer buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mutex slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Bitmask of lower 7 bits used for configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * These bits only can be written when TI_ADS7950_CR_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * is set, otherwise it retains its original state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * [0-3] GPIO signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * [4] Set following frame to return GPIO signal values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * [5] Powers down device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * [6] Sets Vref range1(2.5v) or range2(5v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Bits present on Manual/Auto1/Auto2 commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int cmd_settings_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Bitmask of GPIO command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * [0-3] GPIO direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * [4-6] Different GPIO alarm mode configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * [7] GPIO 2 as device range input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * [8] GPIO 3 as device power down input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * [9] Reset all registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * [10-11] N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int gpio_cmd_settings_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 single_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 single_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ti_ads7950_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum ti_ads7950_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) TI_ADS7950,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) TI_ADS7951,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) TI_ADS7952,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) TI_ADS7953,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) TI_ADS7954,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) TI_ADS7955,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) TI_ADS7956,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) TI_ADS7957,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) TI_ADS7958,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) TI_ADS7959,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) TI_ADS7960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) TI_ADS7961,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TI_ADS7950_V_CHAN(index, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .channel = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .address = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .datasheet_name = "CH##index", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .scan_index = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .realbits = bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .shift = 12 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) TI_ADS7950_V_CHAN(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TI_ADS7950_V_CHAN(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) TI_ADS7950_V_CHAN(2, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) TI_ADS7950_V_CHAN(3, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IIO_CHAN_SOFT_TIMESTAMP(4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) TI_ADS7950_V_CHAN(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) TI_ADS7950_V_CHAN(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) TI_ADS7950_V_CHAN(2, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) TI_ADS7950_V_CHAN(3, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) TI_ADS7950_V_CHAN(4, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TI_ADS7950_V_CHAN(5, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) TI_ADS7950_V_CHAN(6, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) TI_ADS7950_V_CHAN(7, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IIO_CHAN_SOFT_TIMESTAMP(8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) TI_ADS7950_V_CHAN(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TI_ADS7950_V_CHAN(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) TI_ADS7950_V_CHAN(2, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) TI_ADS7950_V_CHAN(3, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) TI_ADS7950_V_CHAN(4, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) TI_ADS7950_V_CHAN(5, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) TI_ADS7950_V_CHAN(6, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) TI_ADS7950_V_CHAN(7, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TI_ADS7950_V_CHAN(8, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) TI_ADS7950_V_CHAN(9, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TI_ADS7950_V_CHAN(10, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) TI_ADS7950_V_CHAN(11, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IIO_CHAN_SOFT_TIMESTAMP(12), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) TI_ADS7950_V_CHAN(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) TI_ADS7950_V_CHAN(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) TI_ADS7950_V_CHAN(2, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TI_ADS7950_V_CHAN(3, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TI_ADS7950_V_CHAN(4, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) TI_ADS7950_V_CHAN(5, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) TI_ADS7950_V_CHAN(6, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) TI_ADS7950_V_CHAN(7, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) TI_ADS7950_V_CHAN(8, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TI_ADS7950_V_CHAN(9, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) TI_ADS7950_V_CHAN(10, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) TI_ADS7950_V_CHAN(11, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) TI_ADS7950_V_CHAN(12, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) TI_ADS7950_V_CHAN(13, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TI_ADS7950_V_CHAN(14, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TI_ADS7950_V_CHAN(15, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IIO_CHAN_SOFT_TIMESTAMP(16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [TI_ADS7950] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .channels = ti_ads7950_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .num_channels = ARRAY_SIZE(ti_ads7950_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [TI_ADS7951] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .channels = ti_ads7951_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .num_channels = ARRAY_SIZE(ti_ads7951_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [TI_ADS7952] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .channels = ti_ads7952_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .num_channels = ARRAY_SIZE(ti_ads7952_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [TI_ADS7953] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .channels = ti_ads7953_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_channels = ARRAY_SIZE(ti_ads7953_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [TI_ADS7954] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .channels = ti_ads7954_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .num_channels = ARRAY_SIZE(ti_ads7954_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [TI_ADS7955] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .channels = ti_ads7955_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .num_channels = ARRAY_SIZE(ti_ads7955_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [TI_ADS7956] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .channels = ti_ads7956_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .num_channels = ARRAY_SIZE(ti_ads7956_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [TI_ADS7957] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .channels = ti_ads7957_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_channels = ARRAY_SIZE(ti_ads7957_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [TI_ADS7958] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .channels = ti_ads7958_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_channels = ARRAY_SIZE(ti_ads7958_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [TI_ADS7959] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .channels = ti_ads7959_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .num_channels = ARRAY_SIZE(ti_ads7959_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [TI_ADS7960] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .channels = ti_ads7960_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .num_channels = ARRAY_SIZE(ti_ads7960_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [TI_ADS7961] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .channels = ti_ads7961_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_channels = ARRAY_SIZE(ti_ads7961_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * scan mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const unsigned long *active_scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ti_ads7950_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int i, cmd, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) st->tx_buf[len++] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Data for the 1st channel is not returned until the 3rd transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) st->tx_buf[len++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) st->tx_buf[len++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) st->ring_xfer.len = len * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct ti_ads7950_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mutex_lock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = spi_sync(st->spi, &st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mutex_unlock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ti_ads7950_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mutex_lock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) st->single_tx = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = st->single_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mutex_unlock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int ti_ads7950_get_range(struct ti_ads7950_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (st->vref_mv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vref = st->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) vref = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (vref < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) vref /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (st->cmd_settings_bitmask & TI_ADS7950_CR_RANGE_5V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) vref *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct ti_ads7950_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = ti_ads7950_scan_direct(indio_dev, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) chan->scan_type.realbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = ti_ads7950_get_range(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *val2 = (1 << chan->scan_type.realbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct iio_info ti_ads7950_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .read_raw = &ti_ads7950_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .update_scan_mode = ti_ads7950_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void ti_ads7950_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct ti_ads7950_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mutex_lock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) st->cmd_settings_bitmask |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) st->cmd_settings_bitmask &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mutex_unlock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int ti_ads7950_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct ti_ads7950_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mutex_lock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* If set as output, return the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (st->gpio_cmd_settings_bitmask & BIT(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = st->cmd_settings_bitmask & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* GPIO data bit sets SDO bits 12-15 to GPIO input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) st->cmd_settings_bitmask |= TI_ADS7950_CR_GPIO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = ((st->single_rx >> 12) & BIT(offset)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Revert back to original settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) st->cmd_settings_bitmask &= ~TI_ADS7950_CR_GPIO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mutex_unlock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int ti_ads7950_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ti_ads7950_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Bitmask is inverted from GPIO framework 0=input/1=output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return !(st->gpio_cmd_settings_bitmask & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int _ti_ads7950_set_direction(struct gpio_chip *chip, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct ti_ads7950_state *st = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mutex_lock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Only change direction if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (input && (st->gpio_cmd_settings_bitmask & BIT(offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) st->gpio_cmd_settings_bitmask &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else if (!input && !(st->gpio_cmd_settings_bitmask & BIT(offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) st->gpio_cmd_settings_bitmask |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mutex_unlock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int ti_ads7950_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return _ti_ads7950_set_direction(chip, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int ti_ads7950_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ti_ads7950_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return _ti_ads7950_set_direction(chip, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int ti_ads7950_init_hw(struct ti_ads7950_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mutex_lock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Settings for Manual/Auto1/Auto2 commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Default to 5v ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) st->cmd_settings_bitmask = TI_ADS7950_CR_RANGE_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Settings for GPIO command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) st->gpio_cmd_settings_bitmask = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mutex_unlock(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int ti_ads7950_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ti_ads7950_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) const struct ti_ads7950_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spi->bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spi->mode |= SPI_CS_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_err(&spi->dev, "Error in spi setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) indio_dev->channels = info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) indio_dev->num_channels = info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) indio_dev->info = &ti_ads7950_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* build spi ring message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spi_message_init(&st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) st->ring_xfer.tx_buf = &st->tx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) st->ring_xfer.rx_buf = &st->rx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* len will be set later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spi_message_add_tail(&st->ring_xfer, &st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * Setup default message. The sample is read at the end of the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * transfer, then it takes one full cycle to convert the sample and one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * more cycle to send the value. The conversion process is driven by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * the SPI clock, which is why we have 3 transfers. The middle one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * just dummy data sent while the chip is converting the sample that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * was read at the end of the first transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) st->scan_single_xfer[0].tx_buf = &st->single_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) st->scan_single_xfer[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) st->scan_single_xfer[0].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) st->scan_single_xfer[1].tx_buf = &st->single_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) st->scan_single_xfer[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) st->scan_single_xfer[1].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) st->scan_single_xfer[2].rx_buf = &st->single_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) st->scan_single_xfer[2].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spi_message_init_with_transfers(&st->scan_single_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) st->scan_single_xfer, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Use hard coded value for reference voltage in ACPI case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ACPI_COMPANION(&spi->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mutex_init(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) st->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (IS_ERR(st->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(&spi->dev, "Failed to get regulator \"vref\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) goto error_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto error_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &ti_ads7950_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(&spi->dev, "Failed to setup triggered buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = ti_ads7950_init_hw(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(&spi->dev, "Failed to init adc chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto error_cleanup_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(&spi->dev, "Failed to register iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto error_cleanup_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Add GPIO chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) st->chip.label = dev_name(&st->spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) st->chip.parent = &st->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) st->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) st->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) st->chip.ngpio = TI_ADS7950_NUM_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) st->chip.get_direction = ti_ads7950_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) st->chip.direction_input = ti_ads7950_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) st->chip.direction_output = ti_ads7950_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) st->chip.get = ti_ads7950_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) st->chip.set = ti_ads7950_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = gpiochip_add_data(&st->chip, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(&spi->dev, "Failed to init GPIOs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto error_iio_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) error_iio_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) error_cleanup_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) error_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mutex_destroy(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int ti_ads7950_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct ti_ads7950_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) gpiochip_remove(&st->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mutex_destroy(&st->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct spi_device_id ti_ads7950_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { "ads7950", TI_ADS7950 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { "ads7951", TI_ADS7951 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { "ads7952", TI_ADS7952 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { "ads7953", TI_ADS7953 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { "ads7954", TI_ADS7954 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) { "ads7955", TI_ADS7955 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { "ads7956", TI_ADS7956 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { "ads7957", TI_ADS7957 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { "ads7958", TI_ADS7958 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { "ads7959", TI_ADS7959 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { "ads7960", TI_ADS7960 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { "ads7961", TI_ADS7961 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const struct of_device_id ads7950_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MODULE_DEVICE_TABLE(of, ads7950_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static struct spi_driver ti_ads7950_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .name = "ads7950",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .of_match_table = ads7950_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .probe = ti_ads7950_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .remove = ti_ads7950_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .id_table = ti_ads7950_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) module_spi_driver(ti_ads7950_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MODULE_AUTHOR("David Lechner <david@lechnology.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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