Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* TI ADS124S0X chip family driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ADS124S08_CMD_NOP	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ADS124S08_CMD_WAKEUP	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ADS124S08_CMD_PWRDWN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ADS124S08_CMD_RESET	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ADS124S08_CMD_START	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ADS124S08_CMD_STOP	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ADS124S08_CMD_SYOCAL	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ADS124S08_CMD_SYGCAL	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ADS124S08_CMD_SFOCAL	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ADS124S08_CMD_RDATA	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ADS124S08_CMD_RREG	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ADS124S08_CMD_WREG	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ADS124S08_ID_REG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ADS124S08_STATUS	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ADS124S08_INPUT_MUX	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ADS124S08_PGA		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ADS124S08_DATA_RATE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ADS124S08_REF		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ADS124S08_IDACMAG	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ADS124S08_IDACMUX	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ADS124S08_VBIAS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ADS124S08_SYS		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ADS124S08_OFCAL0	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ADS124S08_OFCAL1	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ADS124S08_OFCAL2	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ADS124S08_FSCAL0	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ADS124S08_FSCAL1	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ADS124S08_FSCAL2	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ADS124S08_GPIODAT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ADS124S08_GPIOCON	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* ADS124S0x common channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ADS124S08_AIN0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ADS124S08_AIN1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ADS124S08_AIN2		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ADS124S08_AIN3		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ADS124S08_AIN4		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define ADS124S08_AIN5		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ADS124S08_AINCOM	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* ADS124S08 only channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ADS124S08_AIN6		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ADS124S08_AIN7		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ADS124S08_AIN8		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define ADS124S08_AIN9		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define ADS124S08_AIN10		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ADS124S08_AIN11		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ADS124S08_MAX_CHANNELS	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ADS124S08_POS_MUX_SHIFT	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ADS124S08_INT_REF		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ADS124S08_START_REG_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define ADS124S08_NUM_BYTES_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ADS124S08_START_CONV	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ADS124S08_STOP_CONV	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) enum ads124s_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ADS124S08_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ADS124S06_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) struct ads124s_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) struct ads124s_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	const struct ads124s_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * Used to correctly align data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * Ensure timestamp is naturally aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * Note that the full buffer length may not be needed if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * all channels are enabled, as long as the alignment of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * timestamp is maintained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u8 data[5] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADS124S08_CHAN(index)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.channel = index,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.scan_index = index,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.realbits = 32,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.storagebits = 32,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct iio_chan_spec ads124s06_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ADS124S08_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ADS124S08_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ADS124S08_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ADS124S08_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ADS124S08_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ADS124S08_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct iio_chan_spec ads124s08_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ADS124S08_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ADS124S08_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ADS124S08_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ADS124S08_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ADS124S08_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ADS124S08_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ADS124S08_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ADS124S08_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ADS124S08_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ADS124S08_CHAN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ADS124S08_CHAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ADS124S08_CHAN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct ads124s_chip_info ads124s_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	[ADS124S08_ID] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.channels = ads124s08_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.num_channels = ARRAY_SIZE(ads124s08_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	[ADS124S06_ID] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.channels = ads124s06_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.num_channels = ARRAY_SIZE(ads124s06_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct ads124s_private *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	priv->data[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return spi_write(priv->spi, &priv->data[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct ads124s_private *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	priv->data[0] = ADS124S08_CMD_WREG | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	priv->data[1] = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	priv->data[2] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return spi_write(priv->spi, &priv->data[0], 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int ads124s_reset(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct ads124s_private *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (priv->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		gpiod_set_value(priv->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		gpiod_set_value(priv->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct ads124s_private *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			.tx_buf = &priv->data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			.len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			.cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			.tx_buf = &priv->data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			.rx_buf = &priv->data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			.len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	priv->data[0] = ADS124S08_CMD_RDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return get_unaligned_be24(&priv->data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int ads124s_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			    int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct ads124s_private *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			dev_err(&priv->spi->dev, "Set ADC CH failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			dev_err(&priv->spi->dev, "Start conversions failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		ret = ads124s_read(indio_dev, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			dev_err(&priv->spi->dev, "Read ADC failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		*val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			dev_err(&priv->spi->dev, "Stop conversions failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct iio_info ads124s_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.read_raw = &ads124s_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static irqreturn_t ads124s_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct ads124s_private *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int scan_index, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	for_each_set_bit(scan_index, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			 indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 					scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			dev_err(&priv->spi->dev, "Set ADC CH failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			dev_err(&priv->spi->dev, "Start ADC conversions failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		priv->buffer[j] = ads124s_read(indio_dev, scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			dev_err(&priv->spi->dev, "Stop ADC conversions failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int ads124s_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct ads124s_private *ads124s_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	const struct spi_device_id *spi_id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ads124s_priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 						   "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (IS_ERR(ads124s_priv->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		dev_info(&spi->dev, "Reset GPIO not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ads124s_priv->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	indio_dev->name = spi_id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	indio_dev->channels = ads124s_priv->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	indio_dev->num_channels = ads124s_priv->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	indio_dev->info = &ads124s_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	mutex_init(&ads124s_priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 					      ads124s_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		dev_err(&spi->dev, "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ads124s_reset(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct spi_device_id ads124s_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	{ "ads124s06", ADS124S06_ID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{ "ads124s08", ADS124S08_ID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_DEVICE_TABLE(spi, ads124s_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct of_device_id ads124s_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	{ .compatible = "ti,ads124s06" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	{ .compatible = "ti,ads124s08" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DEVICE_TABLE(of, ads124s_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct spi_driver ads124s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.name	= "ads124s08",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.of_match_table = ads124s_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.probe		= ads124s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.id_table	= ads124s_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) module_spi_driver(ads124s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_AUTHOR("Dan Murphy <dmuprhy@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_DESCRIPTION("TI TI_ADS12S0X ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_LICENSE("GPL v2");