^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADS1015 - Texas Instruments Analog-to-Digital Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * IIO driver for ADS1015 ADC 7-bit I2C slave address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * * 0x48 - ADDR connected to Ground
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * * 0x49 - ADDR connected to Vdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * * 0x4A - ADDR connected to SDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * * 0x4B - ADDR connected to SCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADS1015_DRV_NAME "ads1015"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADS1015_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADS1015_CONV_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADS1015_CFG_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADS1015_LO_THRESH_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADS1015_HI_THRESH_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADS1015_CFG_COMP_QUE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADS1015_CFG_COMP_LAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADS1015_CFG_COMP_POL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADS1015_CFG_COMP_MODE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADS1015_CFG_DR_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADS1015_CFG_MOD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADS1015_CFG_PGA_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADS1015_CFG_MUX_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADS1015_CFG_COMP_POL_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADS1015_CFG_MOD_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Comparator queue and disable field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADS1015_CFG_COMP_DISABLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Comparator polarity field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADS1015_CFG_COMP_POL_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADS1015_CFG_COMP_POL_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Comparator mode field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADS1015_CFG_COMP_MODE_TRAD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADS1015_CFG_COMP_MODE_WINDOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* device operating modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADS1015_CONTINUOUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADS1015_SINGLESHOT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADS1015_SLEEP_DELAY_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADS1015_DEFAULT_PGA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADS1015_DEFAULT_DATA_RATE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADS1015_DEFAULT_CHAN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enum chip_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ADSXXXX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ADS1015,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADS1115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum ads1015_channels {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ADS1015_AIN0_AIN1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ADS1015_AIN0_AIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ADS1015_AIN1_AIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ADS1015_AIN2_AIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADS1015_AIN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ADS1015_AIN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ADS1015_AIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ADS1015_AIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ADS1015_TIMESTAMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const unsigned int ads1015_data_rate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 128, 250, 490, 920, 1600, 2400, 3300, 3300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const unsigned int ads1115_data_rate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 8, 16, 32, 64, 128, 250, 475, 860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Translation from PGA bits to full-scale positive and negative input voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * range in mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int ads1015_fullscale_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 6144, 4096, 2048, 1024, 512, 256, 256, 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Translation from COMP_QUE field value to the number of successive readings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * exceed the threshold values before an interrupt is generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const int ads1015_comp_queue[] = { 1, 2, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct iio_event_spec ads1015_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BIT(IIO_EV_INFO_PERIOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ADS1015_V_CHAN(_chan, _addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .address = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .scan_index = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .shift = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .event_spec = ads1015_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .num_event_specs = ARRAY_SIZE(ads1015_events), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .datasheet_name = "AIN"#_chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .differential = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .address = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .channel2 = _chan2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .scan_index = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .shift = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .event_spec = ads1015_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .num_event_specs = ARRAY_SIZE(ads1015_events), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ADS1115_V_CHAN(_chan, _addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .address = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .scan_index = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .event_spec = ads1015_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .num_event_specs = ARRAY_SIZE(ads1015_events), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .datasheet_name = "AIN"#_chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .differential = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .address = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .channel2 = _chan2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .scan_index = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .event_spec = ads1015_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .num_event_specs = ARRAY_SIZE(ads1015_events), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct ads1015_channel_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int pga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ads1015_thresh_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int comp_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int high_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int low_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct ads1015_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Protects ADC ops, e.g: concurrent sysfs/buffered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * data reads, configuration updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int event_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int comp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int *data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Set to true when the ADC is switched to the continuous-conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * mode and exits from a power-down state. This flag is used to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * getting the stale result from the conversion register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bool conv_invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static bool ads1015_event_channel_enabled(struct ads1015_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return (data->event_channel != ADS1015_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int comp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) WARN_ON(ads1015_event_channel_enabled(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) data->event_channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) data->comp_mode = comp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) data->event_channel = ADS1015_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case ADS1015_CFG_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case ADS1015_LO_THRESH_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case ADS1015_HI_THRESH_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct regmap_config ads1015_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .max_register = ADS1015_HI_THRESH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .writeable_reg = ads1015_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct iio_chan_spec ads1015_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ADS1015_V_CHAN(0, ADS1015_AIN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ADS1015_V_CHAN(1, ADS1015_AIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ADS1015_V_CHAN(2, ADS1015_AIN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ADS1015_V_CHAN(3, ADS1015_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct iio_chan_spec ads1115_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ADS1115_V_CHAN(0, ADS1015_AIN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ADS1115_V_CHAN(1, ADS1015_AIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ADS1115_V_CHAN(2, ADS1015_AIN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ADS1115_V_CHAN(3, ADS1015_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int ads1015_set_power_state(struct ads1015_data *data, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct device *dev = regmap_get_device(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #else /* !CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int ads1015_set_power_state(struct ads1015_data *data, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif /* !CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ret, pga, dr, dr_old, conv_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int old, mask, cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (chan < 0 || chan >= ADS1015_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pga = data->channel_data[chan].pga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dr = data->channel_data[chan].data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ADS1015_CFG_DR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dr << ADS1015_CFG_DR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ads1015_event_channel_enabled(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cfg |= data->thresh_data[chan].comp_queue <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ADS1015_CFG_COMP_QUE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) data->comp_mode <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ADS1015_CFG_COMP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cfg = (old & ~mask) | (cfg & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (old != cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) data->conv_invalid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (data->conv_invalid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) usleep_range(conv_time, conv_time + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) data->conv_invalid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return regmap_read(data->regmap, ADS1015_CONV_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static irqreturn_t ads1015_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Ensure natural alignment of timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) s16 chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) s64 timestamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int chan, ret, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) memset(&scan, 0, sizeof(scan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) chan = find_first_bit(indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) indio_dev->masklength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = ads1015_get_adc_result(data, chan, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) scan.chan = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) iio_push_to_buffers_with_timestamp(indio_dev, &scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int ads1015_set_scale(struct ads1015_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int scale, int uscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int fullscale = div_s64((scale * 1000000LL + uscale) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (chan->scan_type.realbits - 1), 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ads1015_fullscale_range[i] == fullscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) data->channel_data[chan->address].pga = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (data->data_rate[i] == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) data->channel_data[chan].data_rate = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int ads1015_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case IIO_CHAN_INFO_RAW: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int shift = chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ads1015_event_channel_enabled(data) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) data->event_channel != chan->address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto release_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = ads1015_set_power_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto release_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = ads1015_get_adc_result(data, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ads1015_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto release_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *val = sign_extend32(*val >> shift, 15 - shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = ads1015_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto release_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) release_direct:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) idx = data->channel_data[chan->address].pga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *val = ads1015_fullscale_range[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *val2 = chan->scan_type.realbits - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) idx = data->channel_data[chan->address].data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *val = data->data_rate[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int ads1015_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = ads1015_set_scale(data, chan, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = ads1015_set_data_rate(data, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int ads1015_read_event(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum iio_event_direction dir, enum iio_event_info info, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int comp_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *val = (dir == IIO_EV_DIR_RISING) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) data->thresh_data[chan->address].high_thresh :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) data->thresh_data[chan->address].low_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dr = data->channel_data[chan->address].data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) comp_queue = data->thresh_data[chan->address].comp_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) period = ads1015_comp_queue[comp_queue] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) USEC_PER_SEC / data->data_rate[dr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *val = period / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *val2 = period % USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int ads1015_write_event(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) enum iio_event_direction dir, enum iio_event_info info, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int realbits = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) long long period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) data->thresh_data[chan->address].high_thresh = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) data->thresh_data[chan->address].low_thresh = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dr = data->channel_data[chan->address].data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) period = val * USEC_PER_SEC + val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (period <= ads1015_comp_queue[i] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) USEC_PER_SEC / data->data_rate[dr])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) data->thresh_data[chan->address].comp_queue = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int ads1015_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (data->event_channel == chan->address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case IIO_EV_DIR_EITHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int ads1015_enable_event_config(struct ads1015_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) const struct iio_chan_spec *chan, int comp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int low_thresh = data->thresh_data[chan->address].low_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int high_thresh = data->thresh_data[chan->address].high_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ads1015_event_channel_enabled(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (data->event_channel != chan->address ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) low_thresh = max(-1 << (chan->scan_type.realbits - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) high_thresh - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) low_thresh << chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) high_thresh << chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = ads1015_set_power_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ads1015_event_channel_enable(data, chan->address, comp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = ads1015_get_adc_result(data, chan->address, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ads1015_event_channel_disable(data, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ads1015_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int ads1015_disable_event_config(struct ads1015_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) const struct iio_chan_spec *chan, int comp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!ads1015_event_channel_enabled(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (data->event_channel != chan->address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ADS1015_CFG_COMP_QUE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ADS1015_CFG_COMP_DISABLE <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ADS1015_CFG_COMP_QUE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ads1015_event_channel_disable(data, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ads1015_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int ads1015_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Prevent from enabling both buffer and event at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = ads1015_enable_event_config(data, chan, comp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = ads1015_disable_event_config(data, chan, comp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static irqreturn_t ads1015_event_handler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct iio_dev *indio_dev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Clear the latched ALERT/RDY pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (ads1015_event_channel_enabled(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) enum iio_event_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u64 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) IIO_EV_TYPE_THRESH, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Prevent from enabling both buffer and event at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ads1015_event_channel_enabled(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ads1015_set_power_state(iio_priv(indio_dev), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ads1015_set_power_state(iio_priv(indio_dev), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .preenable = ads1015_buffer_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .postdisable = ads1015_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .validate_scan_mask = &iio_validate_scan_mask_onehot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "3 2 1 0.5 0.25 0.125");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) sampling_frequency_available, "128 250 490 920 1600 2400 3300");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) sampling_frequency_available, "8 16 32 64 128 250 475 860");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct attribute *ads1015_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) &iio_const_attr_ads1015_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct attribute_group ads1015_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .attrs = ads1015_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static struct attribute *ads1115_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &iio_const_attr_ads1115_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const struct attribute_group ads1115_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .attrs = ads1115_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const struct iio_info ads1015_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .read_raw = ads1015_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .write_raw = ads1015_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .read_event_value = ads1015_read_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .write_event_value = ads1015_write_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .read_event_config = ads1015_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .write_event_config = ads1015_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .attrs = &ads1015_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct iio_info ads1115_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .read_raw = ads1015_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .write_raw = ads1015_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .read_event_value = ads1015_read_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .write_event_value = ads1015_write_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .read_event_config = ads1015_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .write_event_config = ads1015_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .attrs = &ads1115_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int ads1015_client_get_channels_config(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct fwnode_handle *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int i = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) device_for_each_child_node(dev, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned int pga = ADS1015_DEFAULT_PGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (fwnode_property_read_u32(node, "reg", &pval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_err(dev, "invalid reg on %pfw\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) channel = pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (channel >= ADS1015_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_err(dev, "invalid channel index %d on %pfw\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) channel, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) pga = pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (pga > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_err(dev, "invalid gain on %pfw\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) fwnode_handle_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) data_rate = pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (data_rate > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(dev, "invalid data_rate on %pfw\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) fwnode_handle_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) data->channel_data[channel].pga = pga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) data->channel_data[channel].data_rate = data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return i < 0 ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void ads1015_get_channels_config(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!ads1015_client_get_channels_config(client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* fallback on default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) for (k = 0; k < ADS1015_CHANNELS; ++k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ADS1015_CFG_MOD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mode << ADS1015_CFG_MOD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int ads1015_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct ads1015_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) enum chip_ids chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) indio_dev->name = ADS1015_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) chip = (enum chip_ids)device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (chip == ADSXXXX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) chip = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case ADS1015:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) indio_dev->channels = ads1015_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) indio_dev->info = &ads1015_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) data->data_rate = (unsigned int *) &ads1015_data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case ADS1115:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) indio_dev->channels = ads1115_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) indio_dev->info = &ads1115_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) data->data_rate = (unsigned int *) &ads1115_data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_err(&client->dev, "Unknown chip %d\n", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) data->event_channel = ADS1015_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Set default lower and upper threshold to min and max value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) for (i = 0; i < ADS1015_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int realbits = indio_dev->channels[i].scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) data->thresh_data[i].low_thresh = -1 << (realbits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ads1015_get_channels_config(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_err(&client->dev, "Failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ads1015_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) &ads1015_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_err(&client->dev, "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) unsigned long irq_trig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) irqd_get_trigger_type(irq_get_irq_data(client->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) unsigned int cfg_comp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 1 << ADS1015_CFG_COMP_LAT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) switch (irq_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case IRQF_TRIGGER_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ADS1015_CFG_COMP_POL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case IRQF_TRIGGER_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ADS1015_CFG_COMP_POL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) cfg_comp_mask, cfg_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) NULL, ads1015_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) irq_trig | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) client->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) data->conv_invalid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) pm_runtime_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_err(&client->dev, "Failed to register IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int ads1015_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* power down single shot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int ads1015_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int ads1015_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct ads1015_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) data->conv_invalid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static const struct dev_pm_ops ads1015_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ads1015_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const struct i2c_device_id ads1015_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {"ads1015", ADS1015},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {"ads1115", ADS1115},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MODULE_DEVICE_TABLE(i2c, ads1015_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct of_device_id ads1015_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .compatible = "ti,ads1015",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .data = (void *)ADS1015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .compatible = "ti,ads1115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .data = (void *)ADS1115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MODULE_DEVICE_TABLE(of, ads1015_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static struct i2c_driver ads1015_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .name = ADS1015_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .of_match_table = ads1015_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .pm = &ads1015_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .probe = ads1015_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .remove = ads1015_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .id_table = ads1015_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) module_i2c_driver(ads1015_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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