^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Angelo Compagnucci <angelo.compagnucci@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for Texas Instruments' ADC128S052, ADC122S021 and ADC124S021 ADC chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Datasheets can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * https://www.ti.com/lit/ds/symlink/adc128s052.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * https://www.ti.com/lit/ds/symlink/adc122s021.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * https://www.ti.com/lit/ds/symlink/adc124s021.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct adc128_configuration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct adc128 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 buffer[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int adc128_adc_conversion(struct adc128 *adc, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) adc->buffer[0] = channel << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) adc->buffer[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = spi_write(adc->spi, &adc->buffer, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = spi_read(adc->spi, &adc->buffer, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ((adc->buffer[0] << 8 | adc->buffer[1]) & 0xFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int adc128_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct iio_chan_spec const *channel, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct adc128 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = adc128_adc_conversion(adc, channel->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = regulator_get_voltage(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *val2 = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADC128_VOLTAGE_CHANNEL(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .channel = (num), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct iio_chan_spec adc128s052_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ADC128_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ADC128_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ADC128_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ADC128_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ADC128_VOLTAGE_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ADC128_VOLTAGE_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ADC128_VOLTAGE_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ADC128_VOLTAGE_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct iio_chan_spec adc122s021_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ADC128_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ADC128_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct iio_chan_spec adc124s021_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ADC128_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ADC128_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ADC128_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ADC128_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct adc128_configuration adc128_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { adc128s052_channels, ARRAY_SIZE(adc128s052_channels) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { adc122s021_channels, ARRAY_SIZE(adc122s021_channels) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { adc124s021_channels, ARRAY_SIZE(adc124s021_channels) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct iio_info adc128_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .read_raw = adc128_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int adc128_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct adc128 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (dev_fwnode(&spi->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) config = (unsigned long) device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) config = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) indio_dev->info = &adc128_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) indio_dev->channels = adc128_config[config].channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) indio_dev->num_channels = adc128_config[config].num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) adc->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (IS_ERR(adc->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return PTR_ERR(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto err_disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) err_disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int adc128_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct adc128 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id adc128_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "ti,adc128s052", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .compatible = "ti,adc122s021", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .compatible = "ti,adc122s051", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .compatible = "ti,adc122s101", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .compatible = "ti,adc124s021", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .compatible = "ti,adc124s051", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .compatible = "ti,adc124s101", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_DEVICE_TABLE(of, adc128_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct spi_device_id adc128_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { "adc128s052", 0 }, /* index into adc128_config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { "adc122s021", 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { "adc122s051", 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { "adc122s101", 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { "adc124s021", 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { "adc124s051", 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { "adc124s101", 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_DEVICE_TABLE(spi, adc128_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct acpi_device_id adc128_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { "AANT1280", 2 }, /* ADC124S021 compatible ACPI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_DEVICE_TABLE(acpi, adc128_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct spi_driver adc128_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "adc128s052",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .of_match_table = adc128_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .acpi_match_table = ACPI_PTR(adc128_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .probe = adc128_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .remove = adc128_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .id_table = adc128_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) module_spi_driver(adc128_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_DESCRIPTION("Texas Instruments ADC128S052");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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