^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Datasheet: http://www.ti.com/lit/ds/symlink/adc12138.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADC12138_MODE_AUTO_CAL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADC12138_MODE_READ_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADC12138_MODE_ACQUISITION_TIME_6 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADC12138_MODE_ACQUISITION_TIME_10 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADC12138_MODE_ACQUISITION_TIME_18 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADC12138_MODE_ACQUISITION_TIME_34 0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADC12138_STATUS_CAL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) adc12130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) adc12132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) adc12138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct adc12138 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* conversion clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk *cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* positive analog voltage reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct regulator *vref_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* negative analog voltage reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regulator *vref_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* The number of cclk periods for the S/H's acquisition time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int acquisition_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Maximum size needed: 16x 2 bytes ADC data + 8 bytes timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Less may be need if not all channels are enabled, as long as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the 8 byte alignment of the timestamp is maintained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __be16 data[20] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 tx_buf[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADC12138_VOLTAGE_CHANNEL(chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .channel = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) | BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .scan_index = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .realbits = 13, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .shift = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADC12138_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .channel = (chan1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .channel2 = (chan2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .differential = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) | BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .scan_index = si, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .realbits = 13, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .shift = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct iio_chan_spec adc12132_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ADC12138_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ADC12138_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct iio_chan_spec adc12138_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ADC12138_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ADC12138_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ADC12138_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ADC12138_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ADC12138_VOLTAGE_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ADC12138_VOLTAGE_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ADC12138_VOLTAGE_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ADC12138_VOLTAGE_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ADC12138_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ADC12138_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ADC12138_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ADC12138_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ADC12138_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ADC12138_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) IIO_CHAN_SOFT_TIMESTAMP(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int adc12138_mode_programming(struct adc12138 *adc, u8 mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void *rx_buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct spi_transfer xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .tx_buf = adc->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .rx_buf = adc->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Skip unused bits for ADC12130 and ADC12132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (adc->id != adc12138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mode = (mode & 0xc0) | ((mode & 0x0f) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) adc->tx_buf[0] = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = spi_sync_transfer(adc->spi, &xfer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) memcpy(rx_buf, adc->rx_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int adc12138_read_status(struct adc12138 *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rx_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return (rx_buf[0] << 1) | (rx_buf[1] >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int __adc12138_start_conv(struct adc12138 *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct iio_chan_spec const *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void *data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 mode = (ch_to_mux[channel->channel] << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (channel->differential ? 0 : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return adc12138_mode_programming(adc, mode, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int adc12138_start_conv(struct adc12138 *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct iio_chan_spec const *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 trash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return __adc12138_start_conv(adc, channel, &trash, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int adc12138_start_and_read_conv(struct adc12138 *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct iio_chan_spec const *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __be16 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return __adc12138_start_conv(adc, channel, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int adc12138_read_conv_data(struct adc12138 *adc, __be16 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Issue a read status instruction and read previous conversion data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) value, sizeof(*value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int adc12138_wait_eoc(struct adc12138 *adc, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!wait_for_completion_timeout(&adc->complete, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int adc12138_adc_conversion(struct adc12138 *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct iio_chan_spec const *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __be16 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) reinit_completion(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = adc12138_start_conv(adc, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return adc12138_read_conv_data(adc, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int adc12138_read_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct iio_chan_spec const *channel, int *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int *shift, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct adc12138 *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __be16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = adc12138_adc_conversion(adc, channel, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *value = sign_extend32(be16_to_cpu(data) >> 3, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = regulator_get_voltage(adc->vref_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *value = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!IS_ERR(adc->vref_n)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = regulator_get_voltage(adc->vref_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *value -= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* convert regulator output voltage to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *value /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *shift = channel->scan_type.realbits - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!IS_ERR(adc->vref_n)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *value = regulator_get_voltage(adc->vref_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (*value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* convert regulator output voltage to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *value /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct iio_info adc12138_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .read_raw = adc12138_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int adc12138_init(struct adc12138 *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 trash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) reinit_completion(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = adc12138_mode_programming(adc, ADC12138_MODE_AUTO_CAL, &trash, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* data output at this time has no significance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) status = adc12138_read_status(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) adc12138_wait_eoc(adc, msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) status = adc12138_read_status(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (status & ADC12138_STATUS_CAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_warn(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Auto Cal sequence is still in progress: %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) switch (adc->acquisition_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mode = ADC12138_MODE_ACQUISITION_TIME_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mode = ADC12138_MODE_ACQUISITION_TIME_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case 18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mode = ADC12138_MODE_ACQUISITION_TIME_18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case 34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mode = ADC12138_MODE_ACQUISITION_TIME_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return adc12138_mode_programming(adc, mode, &trash, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static irqreturn_t adc12138_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct adc12138 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __be16 trash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int scan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for_each_set_bit(scan_index, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) const struct iio_chan_spec *scan_chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &indio_dev->channels[scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reinit_completion(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = adc12138_start_and_read_conv(adc, scan_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) i ? &adc->data[i - 1] : &trash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_warn(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "failed to start conversion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_warn(&adc->spi->dev, "wait eoc timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = adc12138_read_conv_data(adc, &adc->data[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_warn(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "failed to get conversion data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) iio_push_to_buffers_with_timestamp(indio_dev, adc->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static irqreturn_t adc12138_eoc_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct iio_dev *indio_dev = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct adc12138 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) complete(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int adc12138_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct adc12138 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) adc->id = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) init_completion(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) indio_dev->info = &adc12138_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) switch (adc->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case adc12130:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case adc12132:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) indio_dev->channels = adc12132_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) indio_dev->num_channels = ARRAY_SIZE(adc12132_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case adc12138:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) indio_dev->channels = adc12138_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) indio_dev->num_channels = ARRAY_SIZE(adc12138_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = of_property_read_u32(spi->dev.of_node, "ti,acquisition-time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &adc->acquisition_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) adc->acquisition_time = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) adc->cclk = devm_clk_get(&spi->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(adc->cclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return PTR_ERR(adc->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) adc->vref_p = devm_regulator_get(&spi->dev, "vref-p");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (IS_ERR(adc->vref_p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return PTR_ERR(adc->vref_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) adc->vref_n = devm_regulator_get_optional(&spi->dev, "vref-n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (IS_ERR(adc->vref_n)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Assume vref_n is 0V if an optional regulator is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * specified, otherwise return the error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = PTR_ERR(adc->vref_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = devm_request_irq(&spi->dev, spi->irq, adc12138_eoc_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) IRQF_TRIGGER_RISING, indio_dev->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = clk_prepare_enable(adc->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = regulator_enable(adc->vref_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!IS_ERR(adc->vref_n)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = regulator_enable(adc->vref_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto err_vref_p_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = adc12138_init(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err_vref_n_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) adc12138_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto err_vref_n_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto err_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) err_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err_vref_n_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!IS_ERR(adc->vref_n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) regulator_disable(adc->vref_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) err_vref_p_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) regulator_disable(adc->vref_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk_disable_unprepare(adc->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int adc12138_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct adc12138 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!IS_ERR(adc->vref_n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regulator_disable(adc->vref_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regulator_disable(adc->vref_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clk_disable_unprepare(adc->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct of_device_id adc12138_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { .compatible = "ti,adc12130", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { .compatible = "ti,adc12132", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { .compatible = "ti,adc12138", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DEVICE_TABLE(of, adc12138_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct spi_device_id adc12138_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { "adc12130", adc12130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { "adc12132", adc12132 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { "adc12138", adc12138 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DEVICE_TABLE(spi, adc12138_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct spi_driver adc12138_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "adc12138",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .of_match_table = of_match_ptr(adc12138_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .probe = adc12138_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .remove = adc12138_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .id_table = adc12138_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) module_spi_driver(adc12138_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_DESCRIPTION("ADC12130/ADC12132/ADC12138 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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