Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Axis Communications AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Driver for Texas Instruments' ADC084S021 ADC chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Datasheets can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * https://www.ti.com/lit/ds/symlink/adc084s021.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ADC084S021_DRIVER_NAME "adc084s021"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct adc084s021 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct spi_message message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct spi_transfer spi_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	/* Buffer used to align data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		__be16 channels[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		s64 ts __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	} scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	 * transfer buffers to live in their own cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u16 tx_buf[4] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	__be16 rx_buf[5]; /* First 16-bits are trash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ADC084S021_VOLTAGE_CHANNEL(num)                  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{                                                      \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.type = IIO_VOLTAGE,                                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.channel = (num),                                    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.indexed = 1,                                        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.scan_index = (num),                                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.scan_type = {                                       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			.sign = 'u',                                       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			.realbits = 8,                                     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			.storagebits = 16,                                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			.shift = 4,                                        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.endianness = IIO_BE,                              \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		},                                                   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static const struct iio_chan_spec adc084s021_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ADC084S021_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ADC084S021_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ADC084S021_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ADC084S021_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * Read an ADC channel and return its value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * @adc: The ADC SPI data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * @data: Buffer for converted data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int adc084s021_adc_conversion(struct adc084s021 *adc, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u16 *p = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Do the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ret = spi_sync(adc->spi, &adc->message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	for (; i < n_words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		*(p + i) = adc->rx_buf[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int adc084s021_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			   struct iio_chan_spec const *channel, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			   int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct adc084s021 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		adc->tx_buf[0] = channel->channel << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		ret = adc084s021_adc_conversion(adc, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		*val = be16_to_cpu(*val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		*val = (*val >> channel->scan_type.shift) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		ret = regulator_get_voltage(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		*val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * Read enabled ADC channels and push data to the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * @irq: The interrupt number (not used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * @pollfunc: Pointer to the poll func.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static irqreturn_t adc084s021_buffer_trigger_handler(int irq, void *pollfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct iio_poll_func *pf = pollfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct adc084s021 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (adc084s021_adc_conversion(adc, adc->scan.channels) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		dev_err(&adc->spi->dev, "Failed to read data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					   iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int adc084s021_buffer_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct adc084s021 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int scan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	for_each_set_bit(scan_index, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			 indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		const struct iio_chan_spec *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			&indio_dev->channels[scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		adc->tx_buf[i++] = channel->channel << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	adc->spi_trans.len = 2 + (i * sizeof(__be16)); /* Trash + channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int adc084s021_buffer_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct adc084s021 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	adc->spi_trans.len = 4; /* Trash + single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct iio_info adc084s021_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.read_raw = adc084s021_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.preenable = adc084s021_buffer_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.postdisable = adc084s021_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int adc084s021_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct adc084s021 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dev_err(&spi->dev, "Failed to allocate IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Connect the SPI device and the iio dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* Initiate the Industrial I/O device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	indio_dev->info = &adc084s021_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	indio_dev->channels = adc084s021_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	indio_dev->num_channels = ARRAY_SIZE(adc084s021_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Create SPI transfer for channel reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	adc->spi_trans.tx_buf = adc->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	adc->spi_trans.rx_buf = adc->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	adc->spi_trans.len = 4; /* Trash + single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	spi_message_init_with_transfers(&adc->message, &adc->spi_trans, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	adc->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (IS_ERR(adc->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return PTR_ERR(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/* Setup triggered buffer with pollfunction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 					    adc084s021_buffer_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					    &adc084s021_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(&spi->dev, "Failed to setup triggered buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct of_device_id adc084s021_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	{ .compatible = "ti,adc084s021", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_DEVICE_TABLE(of, adc084s021_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct spi_device_id adc084s021_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	{ ADC084S021_DRIVER_NAME, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_DEVICE_TABLE(spi, adc084s021_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct spi_driver adc084s021_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.name = ADC084S021_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.of_match_table = adc084s021_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.probe = adc084s021_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.id_table = adc084s021_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) module_spi_driver(adc084s021_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Mårten Lindahl <martenli@axis.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DESCRIPTION("Texas Instruments ADC084S021");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_VERSION("1.0");