Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Datasheet: https://www.ti.com/lit/ds/symlink/adc0832-n.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	adc0831,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	adc0832,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	adc0834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	adc0838,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct adc0832 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u8 mux_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	 * Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 * May be shorter if not all channels are enabled subject
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	 * to the timestamp remaining 8 byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u8 data[24] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 tx_buf[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8 rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ADC0832_VOLTAGE_CHANNEL(chan)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.channel = chan,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.scan_index = chan,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.realbits = 8,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			.storagebits = 8,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ADC0832_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.channel = (chan1),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.channel2 = (chan2),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.differential = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.scan_index = si,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			.realbits = 8,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			.storagebits = 8,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const struct iio_chan_spec adc0831_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const struct iio_chan_spec adc0832_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ADC0832_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ADC0832_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static const struct iio_chan_spec adc0834_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ADC0832_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ADC0832_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ADC0832_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ADC0832_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct iio_chan_spec adc0838_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ADC0832_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ADC0832_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ADC0832_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ADC0832_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ADC0832_VOLTAGE_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ADC0832_VOLTAGE_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ADC0832_VOLTAGE_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ADC0832_VOLTAGE_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ADC0832_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ADC0832_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ADC0832_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ADC0832_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	IIO_CHAN_SOFT_TIMESTAMP(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int adc0831_adc_conversion(struct adc0832 *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct spi_device *spi = adc->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ret = spi_read(spi, &adc->rx_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * Skip TRI-STATE and a leading zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int adc0832_adc_conversion(struct adc0832 *adc, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				bool differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct spi_device *spi = adc->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct spi_transfer xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.tx_buf = adc->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.rx_buf = adc->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!adc->mux_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return adc0831_adc_conversion(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	adc->tx_buf[0] = 1 << (adc->mux_bits + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* single-ended or differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	adc->tx_buf[0] |= differential ? 0 : (1 << adc->mux_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* odd / sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	adc->tx_buf[0] |= (channel % 2) << (adc->mux_bits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (adc->mux_bits > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		adc->tx_buf[0] |= channel / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* align Data output BIT7 (MSB) to 8-bit boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	adc->tx_buf[0] <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = spi_sync_transfer(spi, &xfer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return adc->rx_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int adc0832_read_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			struct iio_chan_spec const *channel, int *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			int *shift, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct adc0832 *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		*value = adc0832_adc_conversion(adc, channel->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 						channel->differential);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (*value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			return *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		*value = regulator_get_voltage(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (*value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			return *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		/* convert regulator output voltage to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		*value /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		*shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct iio_info adc0832_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.read_raw = adc0832_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static irqreturn_t adc0832_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct adc0832 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int scan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	for_each_set_bit(scan_index, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			 indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		const struct iio_chan_spec *scan_chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				&indio_dev->channels[scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		int ret = adc0832_adc_conversion(adc, scan_chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 						 scan_chan->differential);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			dev_warn(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				 "failed to get conversion data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		adc->data[i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	iio_push_to_buffers_with_timestamp(indio_dev, adc->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 					   iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int adc0832_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct adc0832 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	indio_dev->info = &adc0832_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	switch (spi_get_device_id(spi)->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case adc0831:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		adc->mux_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		indio_dev->channels = adc0831_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		indio_dev->num_channels = ARRAY_SIZE(adc0831_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	case adc0832:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		adc->mux_bits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		indio_dev->channels = adc0832_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		indio_dev->num_channels = ARRAY_SIZE(adc0832_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case adc0834:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		adc->mux_bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		indio_dev->channels = adc0834_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		indio_dev->num_channels = ARRAY_SIZE(adc0834_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case adc0838:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		adc->mux_bits = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		indio_dev->channels = adc0838_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		indio_dev->num_channels = ARRAY_SIZE(adc0838_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	adc->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (IS_ERR(adc->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return PTR_ERR(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 					 adc0832_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		goto err_reg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		goto err_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) err_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) err_reg_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int adc0832_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct adc0832 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct of_device_id adc0832_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{ .compatible = "ti,adc0831", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ .compatible = "ti,adc0832", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	{ .compatible = "ti,adc0834", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	{ .compatible = "ti,adc0838", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DEVICE_TABLE(of, adc0832_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct spi_device_id adc0832_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ "adc0831", adc0831 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{ "adc0832", adc0832 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ "adc0834", adc0834 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ "adc0838", adc0838 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DEVICE_TABLE(spi, adc0832_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct spi_driver adc0832_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.name = "adc0832",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.of_match_table = adc0832_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.probe = adc0832_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.remove = adc0832_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.id_table = adc0832_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) module_spi_driver(adc0832_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_DESCRIPTION("ADC0831/ADC0832/ADC0834/ADC0838 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_LICENSE("GPL v2");