Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* ADC driver for sunxi platforms' (A10, A13 and A31) GPADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * The Allwinner SoCs all have an ADC that can also act as a touchscreen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * controller and a thermal sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * The thermal sensor works only when the ADC acts as a touchscreen controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * and is configured to throw an interrupt every fixed periods of time (let say
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * every X seconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * One would be tempted to disable the IP on the hardware side rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * disabling interrupts to save some power but that resets the internal clock of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * the IP, resulting in having to wait X seconds every time we want to read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * value of the thermal sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * This is also the reason of using autosuspend in pm_runtime. If there was no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * autosuspend, the thermal sensor would need X seconds after every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * pm_runtime_get_sync to get a value from the ADC. The autosuspend allows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * thermal sensor to be requested again in a certain time span before it gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * shutdown for not being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/iio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/mfd/sun4i-gpadc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static unsigned int sun4i_gpadc_chan_select(unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct gpadc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int		temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int		temp_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned int	tp_mode_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int	tp_adc_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int	(*adc_chan_select)(unsigned int chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned int	adc_chan_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const struct gpadc_data sun4i_gpadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.temp_offset = -1932,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.temp_scale = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.adc_chan_select = &sun4i_gpadc_chan_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct gpadc_data sun5i_gpadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.temp_offset = -1447,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.temp_scale = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.adc_chan_select = &sun4i_gpadc_chan_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct gpadc_data sun6i_gpadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.temp_offset = -1623,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.temp_scale = 167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.adc_chan_select = &sun6i_gpadc_chan_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static const struct gpadc_data sun8i_a33_gpadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.temp_offset = -1662,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.temp_scale = 162,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) struct sun4i_gpadc_iio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct iio_dev			*indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct completion		completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int				temp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32				adc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct regmap			*regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned int			fifo_data_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	atomic_t			ignore_fifo_data_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned int			temp_data_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	atomic_t			ignore_temp_data_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	const struct gpadc_data		*data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bool				no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* prevents concurrent reads of temperature and ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct mutex			mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct thermal_zone_device	*tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct device			*sensor_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.channel = _channel,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.datasheet_name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct iio_map sun4i_gpadc_hwmon_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.adc_channel_label = "temp_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.consumer_dev_name = "iio_hwmon.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct iio_chan_spec sun4i_gpadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				      BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				      BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.datasheet_name = "temp_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				      BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				      BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.datasheet_name = "temp_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regmap_config sun4i_gpadc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				 unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	pm_runtime_get_sync(indio_dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ret = regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			   SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			   SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = regmap_read(info->regmap, SUN4I_GPADC_CTRL1, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (irq == info->fifo_data_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				   info->data->tp_mode_en |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				   info->data->tp_adc_select |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				   info->data->adc_chan_select(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		 * When the IP changes channel, it needs a bit of time to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		 * correct values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		if ((reg & info->data->adc_chan_mask) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			 info->data->adc_chan_select(channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 * The temperature sensor returns valid data only when the ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		 * operates in touchscreen mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				   info->data->tp_mode_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * When the IP changes mode between ADC or touchscreen, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * needs a bit of time to get correct values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if ((reg & info->data->tp_adc_select) != info->data->tp_adc_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int sun4i_gpadc_read(struct iio_dev *indio_dev, int channel, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			    unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	mutex_lock(&info->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = sun4i_prepare_for_irq(indio_dev, channel, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * The temperature sensor throws an interruption periodically (currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * set at periods of ~0.6s in sun4i_gpadc_runtime_resume). A 1s delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * makes sure an interruption occurs in normal conditions. If it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * occur, then there is a timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!wait_for_completion_timeout(&info->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					 msecs_to_jiffies(1000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (irq == info->fifo_data_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		*val = info->adc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		*val = info->temp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	pm_runtime_mark_last_busy(indio_dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	pm_runtime_put_autosuspend(indio_dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	mutex_unlock(&info->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return sun4i_gpadc_read(indio_dev, channel, val, info->fifo_data_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (info->no_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		pm_runtime_get_sync(indio_dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		pm_runtime_mark_last_busy(indio_dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		pm_runtime_put_autosuspend(indio_dev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	*val = info->data->temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int sun4i_gpadc_temp_scale(struct iio_dev *indio_dev, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	*val = info->data->temp_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 				int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		ret = sun4i_gpadc_temp_offset(indio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		if (chan->type == IIO_VOLTAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			ret = sun4i_gpadc_adc_read(indio_dev, chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 						   val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			ret = sun4i_gpadc_temp_read(indio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		if (chan->type == IIO_VOLTAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			/* 3000mV / 4096 * raw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			*val2 = 732421875;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ret = sun4i_gpadc_temp_scale(indio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct iio_info sun4i_gpadc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.read_raw = sun4i_gpadc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	struct sun4i_gpadc_iio *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (atomic_read(&info->ignore_temp_data_irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (!regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, &info->temp_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct sun4i_gpadc_iio *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (atomic_read(&info->ignore_fifo_data_irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (!regmap_read(info->regmap, SUN4I_GPADC_DATA, &info->adc_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int sun4i_gpadc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* Disable the ADC on IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	/* Disable temperature sensor on IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	regmap_write(info->regmap, SUN4I_GPADC_TPR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int sun4i_gpadc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/* clkin = 6MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		     SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		     SUN4I_GPADC_CTRL0_FS_DIV(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		     SUN4I_GPADC_CTRL0_T_ACQ(63));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	regmap_write(info->regmap, SUN4I_GPADC_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		     SUN4I_GPADC_CTRL3_FILTER_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		     SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	/* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~0.6s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	regmap_write(info->regmap, SUN4I_GPADC_TPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		     SUN4I_GPADC_TPR_TEMP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		     SUN4I_GPADC_TPR_TEMP_PERIOD(800));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int sun4i_gpadc_get_temp(void *data, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct sun4i_gpadc_iio *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	int val, scale, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if (sun4i_gpadc_temp_read(info->indio_dev, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	sun4i_gpadc_temp_scale(info->indio_dev, &scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	sun4i_gpadc_temp_offset(info->indio_dev, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	*temp = (val + offset) * scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct thermal_zone_of_device_ops sun4i_ts_tz_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.get_temp = &sun4i_gpadc_get_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct dev_pm_ops sun4i_gpadc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.runtime_suspend = &sun4i_gpadc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.runtime_resume = &sun4i_gpadc_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int sun4i_irq_init(struct platform_device *pdev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			  irq_handler_t handler, const char *devname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			  unsigned int *irq, atomic_t *atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct sun4i_gpadc_dev *mfd_dev = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	 * Once the interrupt is activated, the IP continuously performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	 * conversions thus throws interrupts. The interrupt is activated right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	 * after being requested but we want to control when these interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	 * occur thus we disable it right after being requested. However, an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	 * interrupt might occur between these two instructions and we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	 * make sure that does not happen, by using atomic flags. We set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	 * flag before requesting the interrupt and unset it right after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	 * disabling the interrupt. When an interrupt occurs between these two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	 * instructions, reading the atomic flag will tell us to ignore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	 * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	atomic_set(atomic, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	ret = platform_get_irq_byname(pdev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	ret = regmap_irq_get_virq(mfd_dev->regmap_irqc, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		dev_err(&pdev->dev, "failed to get virq for irq %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	*irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	ret = devm_request_any_context_irq(&pdev->dev, *irq, handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 					   devname, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		dev_err(&pdev->dev, "could not request %s interrupt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 			name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	disable_irq(*irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	atomic_set(atomic, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct of_device_id sun4i_gpadc_of_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		.compatible = "allwinner,sun8i-a33-ths",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		.data = &sun8i_a33_gpadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 				struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	info->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	if (!info->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	info->no_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	indio_dev->channels = sun8i_a33_gpadc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	info->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 					     &sun4i_gpadc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (IS_ERR(info->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		ret = PTR_ERR(info->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (IS_ENABLED(CONFIG_THERMAL_OF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		info->sensor_device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 				 struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	struct sun4i_gpadc_dev *sun4i_gpadc_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	info->no_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	info->regmap = sun4i_gpadc_dev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	indio_dev->channels = sun4i_gpadc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	info->data = (struct gpadc_data *)platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	 * Since the controller needs to be in touchscreen mode for its thermal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	 * sensor to operate properly, and that switching between the two modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	 * needs a delay, always registering in the thermal framework will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	 * significantly slow down the conversion rate of the ADCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	 * Therefore, instead of depending on THERMAL_OF in Kconfig, we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	 * register the sensor if that option is enabled, eventually leaving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	 * that choice to the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	if (IS_ENABLED(CONFIG_THERMAL_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		 * This driver is a child of an MFD which has a node in the DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 		 * but not its children, because of DT backward compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		 * for A10, A13 and A31 SoCs. Therefore, the resulting devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		 * of this driver do not have an of_node variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		 * However, its parent (the MFD driver) has an of_node variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		 * and since devm_thermal_zone_of_sensor_register uses its first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		 * argument to match the phandle defined in the node of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		 * thermal driver with the of_node of the device passed as first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		 * argument and the third argument to call ops from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 		 * thermal_zone_of_device_ops, the solution is to use the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		 * device as first argument to match the phandle with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		 * of_node, and the device from this driver as third argument to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		 * return the temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		info->sensor_device = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		indio_dev->num_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 			ARRAY_SIZE(sun4i_gpadc_channels_no_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		indio_dev->channels = sun4i_gpadc_channels_no_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	if (IS_ENABLED(CONFIG_THERMAL_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		ret = sun4i_irq_init(pdev, "TEMP_DATA_PENDING",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 				     sun4i_gpadc_temp_data_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 				     "temp_data", &info->temp_data_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 				     &info->ignore_temp_data_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	ret = sun4i_irq_init(pdev, "FIFO_DATA_PENDING",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 			     sun4i_gpadc_fifo_data_irq_handler, "fifo_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 			     &info->fifo_data_irq, &info->ignore_fifo_data_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	if (IS_ENABLED(CONFIG_THERMAL_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		ret = iio_map_array_register(indio_dev, sun4i_gpadc_hwmon_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 				"failed to register iio map array\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int sun4i_gpadc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	struct sun4i_gpadc_iio *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	mutex_init(&info->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	info->indio_dev = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	init_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	indio_dev->info = &sun4i_gpadc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 		ret = sun4i_gpadc_probe_dt(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 		ret = sun4i_gpadc_probe_mfd(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	pm_runtime_set_autosuspend_delay(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 					 SUN4I_GPADC_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	if (IS_ENABLED(CONFIG_THERMAL_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 		info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 							    0, info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 							    &sun4i_ts_tz_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 		 * Do not fail driver probing when failing to register in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 		 * thermal because no thermal DT node is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 		if (IS_ERR(info->tzd) && PTR_ERR(info->tzd) != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 				"could not register thermal sensor: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 				PTR_ERR(info->tzd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 			return PTR_ERR(info->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	ret = devm_iio_device_register(&pdev->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 		dev_err(&pdev->dev, "could not register the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 		goto err_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) err_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 		iio_map_array_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int sun4i_gpadc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 	struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	if (!IS_ENABLED(CONFIG_THERMAL_OF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	thermal_zone_of_sensor_unregister(info->sensor_device, info->tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	if (!info->no_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 		iio_map_array_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct platform_device_id sun4i_gpadc_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	{ "sun4i-a10-gpadc-iio", (kernel_ulong_t)&sun4i_gpadc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	{ "sun5i-a13-gpadc-iio", (kernel_ulong_t)&sun5i_gpadc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	{ "sun6i-a31-gpadc-iio", (kernel_ulong_t)&sun6i_gpadc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MODULE_DEVICE_TABLE(platform, sun4i_gpadc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct platform_driver sun4i_gpadc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		.name = "sun4i-gpadc-iio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 		.of_match_table = sun4i_gpadc_of_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 		.pm = &sun4i_gpadc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	.id_table = sun4i_gpadc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 	.probe = sun4i_gpadc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 	.remove = sun4i_gpadc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) module_platform_driver(sun4i_gpadc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MODULE_DESCRIPTION("ADC driver for sunxi platforms");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MODULE_LICENSE("GPL v2");