^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IIO driver for the Apex Embedded Systems STX104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 William Breathitt Gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STX104_OUT_CHAN(chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .channel = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .output = 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STX104_IN_CHAN(chan, diff) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .channel = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .channel2 = chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .differential = diff \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STX104_NUM_OUT_CHAN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STX104_EXTENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned int base[max_num_isa_dev(STX104_EXTENT)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static unsigned int num_stx104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) module_param_hw_array(base, uint, ioport, &num_stx104, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * struct stx104_iio - IIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @chan_out_states: channels' output states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @base: base port address of the IIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct stx104_iio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * struct stx104_gpio - GPIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @chip: instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @lock: synchronization lock to prevent I/O race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @base: base port address of the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @out_state: output bits state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct stx104_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int out_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int stx104_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct iio_chan_spec const *chan, int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct stx104_iio *const priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int adc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int adbu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case IIO_CHAN_INFO_HARDWAREGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* get gain configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) adc_config = inb(priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) gain = adc_config & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *val = 1 << gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (chan->output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *val = priv->chan_out_states[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* select ADC channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) outb(chan->channel | (chan->channel << 4), priv->base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* trigger ADC sample capture and wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) outb(0, priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while (inb(priv->base + 8) & BIT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *val = inw(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* get ADC bipolar/unipolar configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) adc_config = inb(priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) adbu = !(adc_config & BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *val = -32768 * adbu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* get ADC bipolar/unipolar and gain configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) adc_config = inb(priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) adbu = !(adc_config & BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) gain = adc_config & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *val = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *val2 = 15 - adbu + gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int stx104_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct stx104_iio *const priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case IIO_CHAN_INFO_HARDWAREGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Only four gain states (x1, x2, x4, x8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) outb(0, priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) outb(1, priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) outb(2, priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outb(3, priv->base + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (chan->output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* DAC can only accept up to a 16-bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if ((unsigned int)val > 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) priv->chan_out_states[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) outw(val, priv->base + 4 + 2 * chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct iio_info stx104_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .read_raw = stx104_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .write_raw = stx104_write_raw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* single-ended input channels configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct iio_chan_spec stx104_channels_sing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) STX104_OUT_CHAN(0), STX104_OUT_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) STX104_IN_CHAN(0, 0), STX104_IN_CHAN(1, 0), STX104_IN_CHAN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) STX104_IN_CHAN(3, 0), STX104_IN_CHAN(4, 0), STX104_IN_CHAN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) STX104_IN_CHAN(6, 0), STX104_IN_CHAN(7, 0), STX104_IN_CHAN(8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) STX104_IN_CHAN(9, 0), STX104_IN_CHAN(10, 0), STX104_IN_CHAN(11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) STX104_IN_CHAN(12, 0), STX104_IN_CHAN(13, 0), STX104_IN_CHAN(14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) STX104_IN_CHAN(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* differential input channels configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct iio_chan_spec stx104_channels_diff[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) STX104_OUT_CHAN(0), STX104_OUT_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) STX104_IN_CHAN(0, 1), STX104_IN_CHAN(1, 1), STX104_IN_CHAN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) STX104_IN_CHAN(3, 1), STX104_IN_CHAN(4, 1), STX104_IN_CHAN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) STX104_IN_CHAN(6, 1), STX104_IN_CHAN(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int stx104_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* GPIO 0-3 are input only, while the rest are output only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (offset < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int stx104_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (offset >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int stx104_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (offset < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) chip->set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (offset >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return !!(inb(stx104gpio->base) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *bits = inb(stx104gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) const unsigned int mask = BIT(offset) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (offset < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock_irqsave(&stx104gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) stx104gpio->out_state |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) stx104gpio->out_state &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) outb(stx104gpio->out_state, stx104gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_unlock_irqrestore(&stx104gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define STX104_NGPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char *stx104_names[STX104_NGPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void stx104_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* verify masked GPIO are output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!(*mask & 0xF0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *mask >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *bits >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) spin_lock_irqsave(&stx104gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) stx104gpio->out_state &= ~*mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) stx104gpio->out_state |= *mask & *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) outb(stx104gpio->out_state, stx104gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_unlock_irqrestore(&stx104gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int stx104_probe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct stx104_iio *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct stx104_gpio *stx104gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) stx104gpio = devm_kzalloc(dev, sizeof(*stx104gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!stx104gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!devm_request_region(dev, base[id], STX104_EXTENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_name(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) base[id], base[id] + STX104_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) indio_dev->info = &stx104_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* determine if differential inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (inb(base[id] + 8) & BIT(5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) indio_dev->channels = stx104_channels_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) indio_dev->num_channels = ARRAY_SIZE(stx104_channels_sing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) indio_dev->channels = stx104_channels_sing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) priv->base = base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* configure device for software trigger operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) outb(0, base[id] + 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* initialize gain setting to x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) outb(0, base[id] + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* initialize DAC output to 0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) outw(0, base[id] + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) outw(0, base[id] + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) stx104gpio->chip.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) stx104gpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) stx104gpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) stx104gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) stx104gpio->chip.ngpio = STX104_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) stx104gpio->chip.names = stx104_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) stx104gpio->chip.get_direction = stx104_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) stx104gpio->chip.direction_input = stx104_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) stx104gpio->chip.direction_output = stx104_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) stx104gpio->chip.get = stx104_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) stx104gpio->chip.set = stx104_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) stx104gpio->base = base[id] + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) stx104gpio->out_state = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spin_lock_init(&stx104gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) err = devm_gpiochip_add_data(dev, &stx104gpio->chip, stx104gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dev, "GPIO registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct isa_driver stx104_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .probe = stx104_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "stx104"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) module_isa_driver(stx104_driver, num_stx104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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