Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  STMicroelectronics STMPE811 IIO ADC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  4 channel, 10/12-bit ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2013-2018 Toradex AG <stefan.agner@toradex.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/stmpe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define STMPE_REG_INT_STA		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define STMPE_REG_ADC_INT_EN		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define STMPE_REG_ADC_INT_STA		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define STMPE_REG_ADC_CTRL1		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define STMPE_REG_ADC_CTRL2		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define STMPE_REG_ADC_CAPT		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define STMPE_REG_ADC_DATA_CH(channel)	(0x30 + 2 * (channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define STMPE_REG_TEMP_CTRL		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define STMPE_TEMP_CTRL_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define STMPE_TEMP_CTRL_ACQ		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define STMPE_TEMP_CTRL_THRES_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define STMPE_START_ONE_TEMP_CONV	(STMPE_TEMP_CTRL_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 					STMPE_TEMP_CTRL_ACQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 					STMPE_TEMP_CTRL_THRES_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define STMPE_REG_TEMP_DATA		0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define STMPE_REG_TEMP_TH		0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define STMPE_ADC_LAST_NR		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define STMPE_TEMP_CHANNEL		(STMPE_ADC_LAST_NR + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define STMPE_ADC_CH(channel)		((1 << (channel)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define STMPE_ADC_TIMEOUT		msecs_to_jiffies(1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct stmpe_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct stmpe *stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* We are allocating plus one for the temperature channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct iio_chan_spec stmpe_adc_iio_channels[STMPE_ADC_LAST_NR + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static int stmpe_read_voltage(struct stmpe_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	info->channel = (u8)chan->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (info->channel > STMPE_ADC_LAST_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	stmpe_reg_write(info->stmpe, STMPE_REG_ADC_CAPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			STMPE_ADC_CH(info->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				STMPE_ADC_CH(info->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	*val = info->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int stmpe_read_temp(struct stmpe_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	info->channel = (u8)chan->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (info->channel != STMPE_TEMP_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	stmpe_reg_write(info->stmpe, STMPE_REG_TEMP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			STMPE_START_ONE_TEMP_CONV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * absolute temp = +V3.3 * value /7.51 [K]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * scale to [milli °C]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	*val = ((449960l * info->value) / 1024l) - 273150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int stmpe_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			  struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			  int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			  int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			  long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct stmpe_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			ret = stmpe_read_voltage(info, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			ret = stmpe_read_temp(info, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		*val = 3300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		*val2 = info->stmpe->mod_12b ? 12 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static irqreturn_t stmpe_adc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct stmpe_adc *info = (struct stmpe_adc *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__be16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (info->channel <= STMPE_ADC_LAST_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		int int_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		int_sta = stmpe_reg_read(info->stmpe, STMPE_REG_ADC_INT_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* Is the interrupt relevant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (!(int_sta & STMPE_ADC_CH(info->channel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		/* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		stmpe_block_read(info->stmpe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			STMPE_REG_ADC_DATA_CH(info->channel), 2, (u8 *) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, int_sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	} else if (info->channel == STMPE_TEMP_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		/* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		stmpe_block_read(info->stmpe, STMPE_REG_TEMP_DATA, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				(u8 *) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	info->value = (u32) be16_to_cpu(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct iio_info stmpe_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.read_raw = &stmpe_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void stmpe_adc_voltage_chan(struct iio_chan_spec *ics, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ics->type = IIO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ics->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ics->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ics->indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ics->channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void stmpe_adc_temp_chan(struct iio_chan_spec *ics, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ics->type = IIO_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ics->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ics->indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ics->channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int stmpe_adc_init_hw(struct stmpe_adc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct stmpe *stmpe = adc->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ret = stmpe_enable(stmpe, STMPE_BLOCK_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(stmpe->dev, "Could not enable clock for ADC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ret = stmpe811_adc_common_init(stmpe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		stmpe_disable(stmpe, STMPE_BLOCK_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* use temp irq for each conversion completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int stmpe_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct stmpe_adc *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u32 norequest_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int irq_temp, irq_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	int num_chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	irq_adc = platform_get_irq_byname(pdev, "STMPE_ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (irq_adc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return irq_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct stmpe_adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		dev_err(&pdev->dev, "failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	mutex_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	init_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = devm_request_threaded_irq(&pdev->dev, irq_adc, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					stmpe_adc_isr, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					"stmpe-adc", info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				irq_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	irq_temp = platform_get_irq_byname(pdev, "STMPE_TEMP_SENS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (irq_temp >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		ret = devm_request_threaded_irq(&pdev->dev, irq_temp, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 						stmpe_adc_isr, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 						"stmpe-adc", info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			dev_warn(&pdev->dev, "failed requesting irq for"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				 " temp sensor, irq = %d\n", irq_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	indio_dev->name		= dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	indio_dev->info		= &stmpe_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	indio_dev->modes	= INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	info->stmpe = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		dev_err(&pdev->dev, "no device tree node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	of_property_read_u32(np, "st,norequest-mask", &norequest_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	for_each_clear_bit(i, (unsigned long *) &norequest_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			   (STMPE_ADC_LAST_NR + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		stmpe_adc_voltage_chan(&info->stmpe_adc_iio_channels[num_chan], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		num_chan++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	stmpe_adc_temp_chan(&info->stmpe_adc_iio_channels[num_chan], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	num_chan++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	indio_dev->channels = info->stmpe_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	indio_dev->num_channels = num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	ret = stmpe_adc_init_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			~(norequest_mask & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			~(norequest_mask & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return devm_iio_device_register(&pdev->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int __maybe_unused stmpe_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct stmpe_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	stmpe_adc_init_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct platform_driver stmpe_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.probe		= stmpe_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.name	= "stmpe-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.pm	= &stmpe_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) module_platform_driver(stmpe_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct of_device_id stmpe_adc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{ .compatible = "st,stmpe-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DEVICE_TABLE(of, stmpe_adc_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DESCRIPTION("STMPEXXX ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_ALIAS("platform:stmpe-adc");