^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is part of STM32 DFSDM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef MDF_STM32_DFSDM__H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MDF_STM32_DFSDM__H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * STM32 DFSDM - global register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ________________________________________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * | Offset | Registers block |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | 0x020 | CHANNEL 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * | ... | ..... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * | 0x0E0 | CHANNEL 7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | 0x200 | FILTER 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | 0x300 | FILTER 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * | 0x400 | FILTER 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Channels register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* CHCFGR1: Channel configuration register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DFSDM_CHCFGR1_CHEN_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* CHCFGR2: Channel configuration register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* AWSCDR: Channel analog watchdog and short circuit detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Filters register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DFSDM_FILTER_BASE_ADR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DFSDM_FILTER_REG_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* CR1 Control register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DFSDM_CR1_DFEN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DFSDM_CR1_JSWSTART_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DFSDM_CR1_JSYNC_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DFSDM_CR1_JSCAN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DFSDM_CR1_JDMAEN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DFSDM_CR1_RSWSTART_MASK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DFSDM_CR1_RCONT_MASK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DFSDM_CR1_RSYNC_MASK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DFSDM_CR1_RDMAEN_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DFSDM_CR1_RCH_MASK GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DFSDM_CR1_FAST_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DFSDM_CR1_AWFSEL_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* CR2: Control register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DFSDM_CR2_IE_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DFSDM_CR2_JEOCIE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DFSDM_CR2_REOCIE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DFSDM_CR2_JOVRIE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DFSDM_CR2_ROVRIE_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DFSDM_CR2_AWDIE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DFSDM_CR2_SCDIE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DFSDM_CR2_CKABIE_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* ISR: Interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DFSDM_ISR_JEOCF_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DFSDM_ISR_REOCF_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DFSDM_ISR_JOVRF_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DFSDM_ISR_ROVRF_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DFSDM_ISR_AWDF_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DFSDM_ISR_JCIP_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DFSDM_ISR_RCIP_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* ICR: Interrupt flag clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DFSDM_ICR_CLRJOVRF_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DFSDM_ICR_CLRROVRF_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DFSDM_ICR_CLRCKABF_CH(v, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DFSDM_ICR_CLRSCDF_CH(v, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* FCR: Filter control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* RDATAR: Filter data register for regular channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DFSDM_DATAR_DATA_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* AWLTR: Filter analog watchdog low threshold register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* AWHTR: Filter analog watchdog low threshold register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* AWSR: Filter watchdog status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* AWCFR: Filter watchdog status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* DFSDM filter order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum stm32_dfsdm_sinc_order {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DFSDM_FASTSINC_ORDER, /* FastSinc filter type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DFSDM_SINC1_ORDER, /* Sinc 1 filter type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DFSDM_SINC2_ORDER, /* Sinc 2 filter type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DFSDM_SINC3_ORDER, /* Sinc 3 filter type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DFSDM_NB_SINC_ORDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @iosr: integrator oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @fosr: filter oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @rshift: output sample right shift (hardware shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @lshift: output sample left shift (software shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @res: output sample resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @bits: output sample resolution in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @max: output sample maximum positive value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct stm32_dfsdm_filter_osr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int iosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int fosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int rshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int lshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u64 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) s32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @ford: filter order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @flo: filter oversampling data table indexed by fast mode flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @sync_mode: filter synchronized with filter 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @fast: filter fast mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct stm32_dfsdm_filter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enum stm32_dfsdm_sinc_order ford;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct stm32_dfsdm_filter_osr flo[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @id: id of the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @type: interface type linked to stm32_dfsdm_chan_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @src: interface type linked to stm32_dfsdm_chan_src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @alt_si: alternative serial input interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct stm32_dfsdm_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int alt_si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @base: control registers base cpu addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @phys_base: DFSDM IP register physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @regmap: regmap for register read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @fl_list: filter resources list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @num_fls: number of filter resources available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @ch_list: channel resources list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @num_chs: number of channel resources available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @spi_master_freq: SPI clock out frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct stm32_dfsdm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) phys_addr_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct stm32_dfsdm_filter *fl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int num_fls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct stm32_dfsdm_channel *ch_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int num_chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int spi_master_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* DFSDM channel serial spi clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum stm32_dfsdm_spi_clk_src {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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