^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is the ADC part of the STM32 DFSDM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/adc/stm32-dfsdm-adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/hw-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/timer/stm32-lptim-trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/timer/stm32-timer-trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "stm32-dfsdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Conversion timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DFSDM_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Oversampling attribute default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DFSDM_DEFAULT_OVERSAMPLING 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Oversampling max values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DFSDM_MAX_INT_OVERSAMPLING 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DFSDM_MAX_FL_OVERSAMPLING 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DFSDM_DATA_MAX BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Data are output as two's complement data in a 24 bit field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Data from filters are in the range +/-2^(n-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * So, the resolution of samples from filter is actually limited to 23 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DFSDM_DATA_RES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Filter configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DFSDM_CR1_JSCAN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum sd_converter_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DFSDM_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DFSDM_IIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct stm32_dfsdm_dev_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int (*init)(struct device *dev, struct iio_dev *indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const struct regmap_config *regmap_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct stm32_dfsdm_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct stm32_dfsdm *dfsdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct stm32_dfsdm_dev_data *dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int fl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int nconv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long smask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* ADC specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int oversamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct iio_hw_consumer *hwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Audio specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int spi_freq; /* SPI bus clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int sample_freq; /* Sample frequency after filter decimation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int (*cb)(const void *data, size_t size, void *cb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void *cb_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int bufi; /* Buffer current position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int buf_sz; /* Buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dma_addr_t dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct stm32_dfsdm_str2field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* DFSDM channel serial interface type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { "SPI_R", 0 }, /* SPI with data on rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { "SPI_F", 1 }, /* SPI with data on falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* DFSDM channel clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* External SPI clock (CLKIN x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Internal SPI clock (CLKOUT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Internal SPI clock divided by 2 (falling edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Internal SPI clock divided by 2 (falling edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int stm32_dfsdm_str2val(const char *str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct stm32_dfsdm_str2field *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct stm32_dfsdm_str2field *p = list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (p = list; p && p->name; p++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!strcmp(p->name, str))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return p->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * struct stm32_dfsdm_trig_info - DFSDM trigger info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @name: name of the trigger, corresponding to its source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @jextsel: trigger signal selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct stm32_dfsdm_trig_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int jextsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* hardware injected trigger enable, edge selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum stm32_dfsdm_jexten {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) STM32_DFSDM_JEXTEN_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) STM32_DFSDM_JEXTEN_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) STM32_DFSDM_JEXTEN_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) STM32_DFSDM_EXTEN_BOTH_EDGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { TIM1_TRGO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { TIM1_TRGO2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { TIM8_TRGO, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { TIM8_TRGO2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { TIM3_TRGO, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { TIM4_TRGO, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { TIM16_OC1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { TIM6_TRGO, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { TIM7_TRGO, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { LPTIM1_OUT, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { LPTIM2_OUT, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { LPTIM3_OUT, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* lookup triggers registered by stm32 timer trigger driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Checking both stm32 timer trigger type and trig name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * should be safe against arbitrary trigger names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if ((is_stm32_timer_trigger(trig) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) is_stm32_lptim_trigger(trig)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return stm32_dfsdm_trigs[i].jextsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int fast, unsigned int oversamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int i, d, fosr, iosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 res, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int bits, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int m = 1; /* multiplication factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int p = fl->ford; /* filter order (ford) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * This function tries to compute filter oversampling and integrator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * oversampling, base on oversampling ratio requested by user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Decimation d depends on the filter order and the oversampling ratios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * ford: filter order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * fosr: filter over sampling ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * iosr: integrator over sampling ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (fl->ford == DFSDM_FASTSINC_ORDER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) m = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) p = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Look for filter and integrator oversampling ratios which allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * to maximize data output resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (fast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) d = fosr * iosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else if (fl->ford == DFSDM_FASTSINC_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) d = fosr * (iosr + 3) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) d = fosr * (iosr - 1 + p) + p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (d > oversamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else if (d != oversamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Check resolution (limited to signed 32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * res <= 2^31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Sincx filters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * res = m * fosr^p x iosr (with m=1, p=ford)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * FastSinc filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * res = m * fosr^p x iosr (with m=2, p=2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) res = fosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) for (i = p - 1; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) res = res * (u64)fosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (res > DFSDM_DATA_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (res > DFSDM_DATA_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) res = res * (u64)m * (u64)iosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (res > DFSDM_DATA_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (res >= flo->res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) flo->res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) flo->fosr = fosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) flo->iosr = iosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bits = fls(flo->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* 8 LBSs in data register contain chan info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) max = flo->res << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* if resolution is not a power of two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (flo->res > BIT(bits - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) max--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) shift = DFSDM_DATA_RES - bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Compute right/left shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Right shift is performed by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * when transferring samples to data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Left shift is done by software on buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (shift > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Resolution is lower than 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) flo->rshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) flo->lshift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * If resolution is 24 bits or more,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * max positive value may be ambiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * (equal to max negative value as sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * bit is dropped).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Reduce resolution to 23 bits (rshift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * to keep the sign on bit 23 and treat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * saturation before rescaling on 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * bits (lshift).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) flo->rshift = 1 - shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) flo->lshift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) max >>= flo->rshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) flo->max = (s32)max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) flo->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __func__, fast, flo->fosr, flo->iosr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) flo->res, bits, flo->rshift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) flo->lshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!flo->res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int oversamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int ret0, ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret0 < 0 && ret1 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "Filter parameters not found: errors %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret0, ret1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) chan = indio_dev->channels + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DFSDM_CHCFGR1_CHEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DFSDM_CHCFGR1_CHEN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) chan = indio_dev->channels + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DFSDM_CHCFGR1_CHEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DFSDM_CHCFGR1_CHEN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct stm32_dfsdm_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int id = ch->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct regmap *regmap = dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DFSDM_CHCFGR1_SITP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DFSDM_CHCFGR1_SITP(ch->type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DFSDM_CHCFGR1_SPICKSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DFSDM_CHCFGR1_SPICKSEL(ch->src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DFSDM_CHCFGR1_CHINSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int fl_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct stm32_dfsdm *dfsdm = adc->dfsdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Enable filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Nothing more to do for injected (scan mode/triggered) conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (adc->nconv > 1 || trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Software start (single or continuous) regular conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DFSDM_CR1_RSWSTART_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DFSDM_CR1_RSWSTART(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int fl_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Disable conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int fl_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* set trigger source and polarity (default to rising edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) jextsel = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DFSDM_CR1_JEXTSEL(jextsel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DFSDM_CR1_JEXTEN(jexten));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int fl_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) fl->fast = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * In continuous mode, use fast mode configuration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * if it provides a better resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (adc->nconv == 1 && !trig &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (fl->flo[1].res >= fl->flo[0].res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) fl->fast = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) flo = &fl->flo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!flo->res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(&indio_dev->dev, "Samples actual resolution: %d bits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) min(flo->bits, (u32)DFSDM_DATA_RES - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for_each_set_bit(bit, &adc->smask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sizeof(adc->smask) * BITS_PER_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) chan = indio_dev->channels + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = regmap_update_bits(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DFSDM_CHCFGR2(chan->channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DFSDM_CHCFGR2_DTRBS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DFSDM_CHCFGR2_DTRBS(flo->rshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned int fl_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int bit, jchg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Average integrator oversampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DFSDM_FCR_IOSR(flo->iosr - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Filter order and Oversampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DFSDM_FCR_FOSR(flo->fosr - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) DFSDM_FCR_FORD(fl->ford));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DFSDM_CR1_FAST_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DFSDM_CR1_FAST(fl->fast));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * DFSDM modes configuration W.R.T audio/iio type modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * ----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Modes | regular | regular | injected | injected |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * | | continuous | | + scan |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * --------------|---------|--------------|----------|------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * single conv | x | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * (1 chan) | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * --------------|---------|--------------|----------|------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * 1 Audio chan | | sample freq | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * | | or sync_mode | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * --------------|---------|--------------|----------|------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * 1 IIO chan | | sample freq | trigger | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * | | or sync_mode | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * --------------|---------|--------------|----------|------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * 2+ IIO chans | | | | trigger or |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * | | | | sync_mode |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * ----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (adc->nconv == 1 && !trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bit = __ffs(adc->smask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) chan = indio_dev->channels + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Use regular conversion for single channel without trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cr1 = DFSDM_CR1_RCH(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Continuous conversions triggered by SPI clk in buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cr1 |= DFSDM_CR1_RCONT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Use injected conversion for multiple channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) for_each_set_bit(bit, &adc->smask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) sizeof(adc->smask) * BITS_PER_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) chan = indio_dev->channels + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) jchg |= BIT(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Use scan mode for multiple channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Continuous conversions not supported in injected mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * either use:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * - conversions in sync with filter 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * - triggered conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!fl->sync_mode && !trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct iio_chan_spec *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct stm32_dfsdm_channel *df_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) const char *of_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int chan_idx = ch->scan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = of_property_read_u32_index(indio_dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "st,adc-channels", chan_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &ch->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) " Error parsing 'st,adc-channels' for idx %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) chan_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ch->channel >= dfsdm->num_chs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) " Error bad channel number %d (max = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ch->channel, dfsdm->num_chs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = of_property_read_string_index(indio_dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "st,adc-channel-names", chan_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) &ch->datasheet_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) " Error parsing 'st,adc-channel-names' for idx %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) chan_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) df_ch = &dfsdm->ch_list[ch->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) df_ch->id = ch->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = of_property_read_string_index(indio_dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "st,adc-channel-types", chan_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &of_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) df_ch->type = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = of_property_read_string_index(indio_dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "st,adc-channel-clk-src", chan_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &of_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) df_ch->src = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = of_property_read_u32_index(indio_dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "st,adc-alt-channel", chan_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &df_ch->alt_si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) df_ch->alt_si = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uintptr_t priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned int sample_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned int spi_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int oversamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (spi_freq % sample_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_dbg(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "Rate not accurate. requested (%u), actual (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) sample_freq, spi_freq / oversamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) adc->sample_freq = spi_freq / oversamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) adc->oversamp = oversamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) uintptr_t priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned int sample_freq = adc->sample_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned int spi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(&indio_dev->dev, "enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* If DFSDM is master on SPI, SPI freq can not be updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = kstrtoint(buf, 0, &spi_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!spi_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (sample_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) adc->spi_freq = spi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = stm32_dfsdm_start_channel(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) goto stop_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto filter_unconfigure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) filter_unconfigure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DFSDM_CR1_CFG_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) stop_channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) stm32_dfsdm_stop_channel(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DFSDM_CR1_CFG_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) stm32_dfsdm_stop_channel(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * DMA cyclic transfers are used, buffer is split into two periods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * There should be :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * - always one buffer (period) DMA is working on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * - one buffer (period) driver pushed to ASoC side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) status = dmaengine_tx_status(adc->dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) adc->dma_chan->cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (status == DMA_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Residue is size in bytes from end of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned int i = adc->buf_sz - state.residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Return available bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (i >= adc->bufi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) size = i - adc->bufi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) size = adc->buf_sz + i - adc->bufi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) s32 *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned int i = adc->nconv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) s32 *ptr = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Mask 8 LSB that contains the channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) *ptr &= 0xFFFFFF00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (*ptr > flo->max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *ptr -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Samples from filter are retrieved with 23 bits resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * or less. Shift left to align MSB on 24 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) *ptr <<= flo->lshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void stm32_dfsdm_dma_buffer_done(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int available = stm32_dfsdm_adc_dma_residue(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) size_t old_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * FIXME: In Kernel interface does not support cyclic DMA buffer,and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * offers only an interface to push data samples per samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * For this reason IIO buffer interface is not used and interface is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * bypassed using a private callback registered by ASoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * This should be a temporary solution waiting a cyclic DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * support in IIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) adc->bufi, available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) old_pos = adc->bufi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) while (available >= indio_dev->scan_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) stm32_dfsdm_process_data(adc, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) available -= indio_dev->scan_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) adc->bufi += indio_dev->scan_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (adc->bufi >= adc->buf_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (adc->cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) adc->cb(&adc->rx_buf[old_pos],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) adc->buf_sz - old_pos, adc->cb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) adc->bufi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) old_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * In DMA mode the trigger services of IIO are not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * (e.g. no call to iio_trigger_poll).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Calling irq handler associated to the hardware trigger is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * relevant as the conversions have already been done. Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * transfers are performed directly in DMA callback instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * This implementation avoids to call trigger irq handler that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * may sleep, in an atomic context (DMA irq handler context).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (adc->dev_data->type == DFSDM_IIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) iio_push_to_buffers(indio_dev, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (adc->cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) adc->cb_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * The DFSDM supports half-word transfers. However, for 16 bits record,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * shift is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct dma_slave_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!adc->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) adc->buf_sz, adc->buf_sz / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (adc->nconv == 1 && !indio_dev->trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) config.src_addr += DFSDM_RDATAR(adc->fl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) config.src_addr += DFSDM_JDATAR(adc->fl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = dmaengine_slave_config(adc->dma_chan, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Prepare a DMA cyclic transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) adc->dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) adc->buf_sz, adc->buf_sz / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) desc->callback = stm32_dfsdm_dma_buffer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) desc->callback_param = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) goto err_stop_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Issue pending DMA requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dma_async_issue_pending(adc->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (adc->nconv == 1 && !indio_dev->trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Enable regular DMA transfer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret = regmap_update_bits(adc->dfsdm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) DFSDM_CR1(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) DFSDM_CR1_RDMAEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DFSDM_CR1_RDMAEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Enable injected DMA transfer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = regmap_update_bits(adc->dfsdm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) DFSDM_CR1(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) DFSDM_CR1_JDMAEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) DFSDM_CR1_JDMAEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) goto err_stop_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) err_stop_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dmaengine_terminate_all(adc->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!adc->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dmaengine_terminate_all(adc->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) const unsigned long *scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) adc->smask = *scan_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* Reset adc buffer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) adc->bufi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (adc->hwc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = iio_hw_consumer_enable(adc->hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto err_stop_hwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = stm32_dfsdm_adc_dma_start(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dev_err(&indio_dev->dev, "Can't start DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) goto stop_dfsdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(&indio_dev->dev, "Can't start conversion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) goto err_stop_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) err_stop_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) stm32_dfsdm_adc_dma_stop(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) stop_dfsdm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) stm32_dfsdm_stop_dfsdm(adc->dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) err_stop_hwc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (adc->hwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) iio_hw_consumer_disable(adc->hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) stm32_dfsdm_stop_conv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) stm32_dfsdm_adc_dma_stop(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) stm32_dfsdm_stop_dfsdm(adc->dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (adc->hwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) iio_hw_consumer_disable(adc->hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .postenable = &stm32_dfsdm_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .predisable = &stm32_dfsdm_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * DMA transfer period is achieved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * @iio_dev: Handle to IIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * @cb: Pointer to callback function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * - data: pointer to data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * - size: size in byte of the data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * - private: pointer to consumer private structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * @private: Pointer to consumer private structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int (*cb)(const void *data, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) void *private),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct stm32_dfsdm_adc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) adc->cb = cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) adc->cb_priv = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * stm32_dfsdm_release_buff_cb - unregister buffer callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * @iio_dev: Handle to IIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct stm32_dfsdm_adc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) adc->cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) adc->cb_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) const struct iio_chan_spec *chan, int *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) reinit_completion(&adc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) adc->buffer = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) goto stop_dfsdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) adc->nconv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) adc->smask = BIT(chan->scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = stm32_dfsdm_start_conv(indio_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto stop_dfsdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) timeout = wait_for_completion_interruptible_timeout(&adc->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) DFSDM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Mask IRQ for regular conversion achievement*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) else if (timeout < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) stm32_dfsdm_stop_conv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) stm32_dfsdm_process_data(adc, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) stop_dfsdm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) stm32_dfsdm_stop_dfsdm(adc->dfsdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) unsigned int spi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) switch (ch->src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) spi_freq = adc->dfsdm->spi_master_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) spi_freq = adc->dfsdm->spi_master_freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) spi_freq = adc->spi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_dbg(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "Sampling rate changed from (%u) to (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) adc->sample_freq, spi_freq / val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) adc->oversamp = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) adc->sample_freq = spi_freq / val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = iio_hw_consumer_enable(adc->hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "%s: IIO enable failed (channel %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) __func__, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) iio_hw_consumer_disable(adc->hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "%s: Conversion failed (channel %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) __func__, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) *val = adc->oversamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) *val = adc->sample_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const struct iio_info stm32_dfsdm_info_audio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .read_raw = stm32_dfsdm_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .write_raw = stm32_dfsdm_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .update_scan_mode = stm32_dfsdm_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const struct iio_info stm32_dfsdm_info_adc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .read_raw = stm32_dfsdm_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .write_raw = stm32_dfsdm_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .update_scan_mode = stm32_dfsdm_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .validate_trigger = stm32_dfsdm_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct iio_dev *indio_dev = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct regmap *regmap = adc->dfsdm->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) unsigned int status, int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (status & DFSDM_ISR_REOCF_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Read the data register clean the IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) complete(&adc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (status & DFSDM_ISR_ROVRF_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (int_en & DFSDM_CR2_ROVRIE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev_warn(&indio_dev->dev, "Overrun detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) DFSDM_ICR_CLRROVRF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) DFSDM_ICR_CLRROVRF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * Define external info for SPI Frequency and audio sampling rate that can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * configured by ASoC driver through consumer.h API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .name = "spi_clk_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .shared = IIO_SHARED_BY_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .read = dfsdm_adc_audio_get_spiclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .write = dfsdm_adc_audio_set_spiclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (adc->dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dma_free_coherent(adc->dma_chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) DFSDM_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) adc->rx_buf, adc->dma_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dma_release_channel(adc->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static int stm32_dfsdm_dma_request(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) adc->dma_chan = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (IS_ERR(adc->dma_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) int ret = PTR_ERR(adc->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) adc->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) DFSDM_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) &adc->dma_buf, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!adc->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dma_release_channel(adc->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct iio_chan_spec *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ch->type = IIO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ch->indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * IIO_CHAN_INFO_RAW: used to compute regular conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) BIT(IIO_CHAN_INFO_SAMP_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (adc->dev_data->type == DFSDM_AUDIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ch->ext_info = dfsdm_adc_audio_ext_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ch->scan_type.shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ch->scan_type.sign = 's';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ch->scan_type.realbits = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ch->scan_type.storagebits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return stm32_dfsdm_chan_configure(adc->dfsdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) &adc->dfsdm->ch_list[ch->channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct iio_chan_spec *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct stm32_dfsdm_channel *d_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ch->scan_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_err(&indio_dev->dev, "Channels init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) d_ch = &adc->dfsdm->ch_list[ch->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) adc->spi_freq = adc->dfsdm->spi_master_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) indio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) indio_dev->channels = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return stm32_dfsdm_dma_request(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct iio_chan_spec *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int num_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int ret, chan_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) "st,adc-channels");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return num_ch < 0 ? num_ch : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Bind to SD modulator IIO device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (IS_ERR(adc->hwc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ch[chan_idx].scan_index = chan_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_err(&indio_dev->dev, "Channels init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) indio_dev->num_channels = num_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) indio_dev->channels = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) init_completion(&adc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Optionally request DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ret = stm32_dfsdm_dma_request(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return dev_err_probe(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) "DMA channel request failed with\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev_dbg(dev, "No DMA support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ret = iio_triggered_buffer_setup(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &iio_pollfunc_store_time, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) &stm32_dfsdm_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) stm32_dfsdm_dma_release(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_err(&indio_dev->dev, "buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* lptimer/timer hardware triggers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .type = DFSDM_IIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .init = stm32_dfsdm_adc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .type = DFSDM_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .init = stm32_dfsdm_audio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const struct of_device_id stm32_dfsdm_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .compatible = "st,stm32-dfsdm-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .data = &stm32h7_dfsdm_adc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .compatible = "st,stm32-dfsdm-dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .data = &stm32h7_dfsdm_audio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct stm32_dfsdm_adc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) const struct stm32_dfsdm_dev_data *dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct iio_dev *iio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int ret, irq, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dev_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) iio = devm_iio_device_alloc(dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (!iio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) adc->dfsdm = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) iio->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) iio->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) platform_set_drvdata(pdev, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_err(dev, "Missing or bad reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (dev_data->type == DFSDM_AUDIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) iio->info = &stm32_dfsdm_info_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) iio->info = &stm32_dfsdm_info_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) iio->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * In a first step IRQs generated for channels are not treated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) 0, pdev->name, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) dev_err(dev, "Failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) dev_err(dev, "Failed to set filter order\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) adc->dfsdm->fl_list[adc->fl_id].ford = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) adc->dev_data = dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ret = dev_data->init(dev, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ret = iio_device_register(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (dev_data->type == DFSDM_AUDIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ret = of_platform_populate(np, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dev_err(dev, "Failed to find an audio DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) err_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) iio_device_unregister(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) err_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) stm32_dfsdm_dma_release(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (adc->dev_data->type == DFSDM_AUDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) of_platform_depopulate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) stm32_dfsdm_dma_release(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) stm32_dfsdm_predisable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct stm32_dfsdm_channel *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* restore channels configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) for (i = 0; i < indio_dev->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) chan = indio_dev->channels + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ch = &adc->dfsdm->ch_list[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) stm32_dfsdm_postenable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static struct platform_driver stm32_dfsdm_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .name = "stm32-dfsdm-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .of_match_table = stm32_dfsdm_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .pm = &stm32_dfsdm_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .probe = stm32_dfsdm_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .remove = stm32_dfsdm_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) module_platform_driver(stm32_dfsdm_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) MODULE_DESCRIPTION("STM32 sigma delta ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags