^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ST SPEAr ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Stefan Roese <sr@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* SPEAR registers definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Bit definitions for SPEAR_ADC_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPEAR_ADC_DATA_MASK 0x03ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPEAR_ADC_DATA_BITS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPEAR_ADC_MOD_NAME "spear-adc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPEAR_ADC_CHANNEL_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPEAR_ADC_CLK_MIN 2500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPEAR_ADC_CLK_MAX 20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct adc_regs_spear3xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 scan_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 clk; /* Not avail for 1340 & 1310 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct chan_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct adc_regs_spear6xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 pad[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 scan_rate_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 scan_rate_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct chan_data average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct spear_adc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 current_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 sampling_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 avg_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 vref_external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Functions to access some SPEAr ADC register. Abstracted into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * static inline functions, because of different register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * on different SoC variants (SPEAr300 vs SPEAr600 etc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writel(val, &st->adc_base_spear6xx->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 clk_high, clk_low, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 apb_clk = clk_get_rate(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) count = DIV_ROUND_UP(apb_clk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_low = count / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_high = count - clk_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) st->current_clk = apb_clk / count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) &st->adc_base_spear6xx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static u32 spear_adc_get_average(struct spear_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (of_device_is_compatible(st->np, "st,spear600-adc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return __raw_readl(&st->adc_base_spear6xx->average.msb) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SPEAR_ADC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return __raw_readl(&st->adc_base_spear3xx->average) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SPEAR_ADC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (of_device_is_compatible(st->np, "st,spear600-adc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &st->adc_base_spear6xx->scan_rate_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &st->adc_base_spear6xx->scan_rate_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int spear_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct spear_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SPEAR_ADC_STATUS_START_CONVERSION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SPEAR_ADC_STATUS_ADC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (st->vref_external == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spear_adc_set_status(st, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) wait_for_completion(&st->completion); /* set by ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *val = st->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *val = st->vref_external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *val2 = SPEAR_ADC_DATA_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *val = st->current_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int spear_adc_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct spear_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (mask != IIO_CHAN_INFO_SAMP_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if ((val < SPEAR_ADC_CLK_MIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (val > SPEAR_ADC_CLK_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (val2 != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spear_adc_set_clk(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SPEAR_ADC_CHAN(idx) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .channel = idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct iio_chan_spec spear_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SPEAR_ADC_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SPEAR_ADC_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SPEAR_ADC_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SPEAR_ADC_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SPEAR_ADC_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SPEAR_ADC_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SPEAR_ADC_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SPEAR_ADC_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static irqreturn_t spear_adc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct spear_adc_state *st = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Read value to clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) st->value = spear_adc_get_average(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) complete(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int spear_adc_configure(struct spear_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Reset ADC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spear_adc_set_status(st, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __raw_writel(0, &st->adc_base_spear6xx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spear_adc_set_ctrl(st, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spear_adc_set_scanrate(st, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spear_adc_set_clk(st, st->sampling_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct iio_info spear_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .read_raw = &spear_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .write_raw = &spear_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int spear_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct spear_adc_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct iio_dev *indio_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(dev, "failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) st->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * SPEAr600 has a different register layout than other SPEAr SoC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * (e.g. SPEAr3xx). Let's provide two register base addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * to support multi-arch kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (IS_ERR(st->adc_base_spear6xx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return PTR_ERR(st->adc_base_spear6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) st->adc_base_spear3xx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) st->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(st->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(dev, "failed getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return PTR_ERR(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = clk_prepare_enable(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(dev, "failed enabling clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto errout2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(dev, "failed requesting interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto errout2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (of_property_read_u32(np, "sampling-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &st->sampling_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(dev, "sampling-frequency missing in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto errout2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Optional avg_samples defaults to 0, resulting in single data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) of_property_read_u32(np, "average-samples", &st->avg_samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Optional vref_external defaults to 0, resulting in internal vref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) of_property_read_u32(np, "vref-external", &st->vref_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spear_adc_configure(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) init_completion(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) indio_dev->name = SPEAR_ADC_MOD_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) indio_dev->info = &spear_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) indio_dev->channels = spear_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto errout2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) errout2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) clk_disable_unprepare(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int spear_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct spear_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_disable_unprepare(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct of_device_id spear_adc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { .compatible = "st,spear600-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct platform_driver spear_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .probe = spear_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .remove = spear_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = SPEAR_ADC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .of_match_table = of_match_ptr(spear_adc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) module_platform_driver(spear_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_DESCRIPTION("SPEAr ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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