^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2018 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* PMIC global registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SC27XX_MODULE_EN 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SC27XX_MODULE_ADC_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SC27XX_ARM_CLK_EN 0xc10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SC27XX_CLK_ADC_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SC27XX_CLK_ADC_CLK_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* ADC controller registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SC27XX_ADC_CTL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SC27XX_ADC_CH_CFG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SC27XX_ADC_DATA 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SC27XX_ADC_INT_EN 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SC27XX_ADC_INT_CLR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SC27XX_ADC_INT_STS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SC27XX_ADC_INT_RAW 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Bits and mask definition for SC27XX_ADC_CTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SC27XX_ADC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SC27XX_ADC_CHN_RUN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SC27XX_ADC_12BIT_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SC27XX_ADC_RUN_NUM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Bits and mask definition for SC27XX_ADC_CH_CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC27XX_ADC_SCALE_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC27XX_ADC_SCALE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Bits definitions for SC27XX_ADC_INT_EN registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC27XX_ADC_IRQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Bits definitions for SC27XX_ADC_INT_CLR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC27XX_ADC_IRQ_CLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Bits definitions for SC27XX_ADC_INT_RAW registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC27XX_ADC_IRQ_RAW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Mask definition for SC27XX_ADC_DATA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC27XX_ADC_DATA_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Timeout (ms) for the trylock of hardware spinlocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC27XX_ADC_HWLOCK_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Timeout (us) for ADC data conversion according to ADC datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC27XX_ADC_RDY_TIMEOUT 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC27XX_ADC_POLL_RAW_STATUS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Maximum ADC channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC27XX_ADC_CHANNEL_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* ADC voltage ratio definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC27XX_VOLT_RATIO(n, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC27XX_RATIO_NUMERATOR_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct sc27xx_adc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * One hardware spinlock to synchronize between the multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * subsystems which will access the unique ADC controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int channel_scale[SC27XX_ADC_CHANNEL_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sc27xx_adc_linear_graph {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int volt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int adc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int volt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int adc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * According to the datasheet, we can convert one ADC value to one voltage value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * through 2 points in the linear graph. If the voltage is less than 1.2v, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * should use the small-scale graph, and if more than 1.2v, we should use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * big-scale graph.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct sc27xx_adc_linear_graph big_scale_graph = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 4200, 3310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 3600, 2832,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct sc27xx_adc_linear_graph small_scale_graph = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 1000, 3413,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 100, 341,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 4200, 856,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 3600, 733,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 1000, 833,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 100, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ((calib_data & 0xff) + calib_adc - 128) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool big_scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct sc27xx_adc_linear_graph *calib_graph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sc27xx_adc_linear_graph *graph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *cell_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 calib_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (big_scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) calib_graph = &big_scale_graph_calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) graph = &big_scale_graph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cell_name = "big_scale_calib";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) calib_graph = &small_scale_graph_calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) graph = &small_scale_graph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cell_name = "small_scale_calib";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cell = nvmem_cell_get(data->dev, cell_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(cell))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) buf = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) memcpy(&calib_data, buf, min(len, sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Only need to calibrate the adc values in the linear graph. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) calib_graph->adc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int sc27xx_adc_get_ratio(int channel, int scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return scale ? SC27XX_VOLT_RATIO(400, 1025) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SC27XX_VOLT_RATIO(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return SC27XX_VOLT_RATIO(7, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return SC27XX_VOLT_RATIO(375, 9000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return scale ? SC27XX_VOLT_RATIO(100, 125) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SC27XX_VOLT_RATIO(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case 19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return SC27XX_VOLT_RATIO(1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return SC27XX_VOLT_RATIO(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return SC27XX_VOLT_RATIO(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int scale, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 tmp, value, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(data->dev, "timeout to get the hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SC27XX_ADC_EN, SC27XX_ADC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto unlock_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Configure the channel id and scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Select 12bit conversion mode, and only sample 1 time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp = SC27XX_ADC_12BIT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = regmap_read_poll_timeout(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) data->base + SC27XX_ADC_INT_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) status, (status & SC27XX_ADC_IRQ_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SC27XX_ADC_POLL_RAW_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SC27XX_ADC_RDY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) value &= SC27XX_ADC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) disable_adc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SC27XX_ADC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unlock_adc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) hwspin_unlock_raw(data->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *val = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int channel, int scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 *div_numerator, u32 *div_denominator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 ratio = sc27xx_adc_get_ratio(channel, scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int raw_adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tmp /= (graph->adc0 - graph->adc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tmp += graph->volt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return tmp < 0 ? 0 : tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int scale, int raw_adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 numerator, denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Convert ADC values to voltage values according to the linear graph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * and channel 5 and channel 1 has been calibrated, so we can just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * return the voltage values calculated by the linear graph. But other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * channels need be calculated to the real voltage values with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * voltage ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return (volt * denominator + numerator / 2) / numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int channel, int scale, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret, raw_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct sc27xx_adc_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int scale = data->channel_scale[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *val = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = sc27xx_adc_read_processed(data, chan->channel, scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *val = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *val = scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct sc27xx_adc_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) data->channel_scale[chan->channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct iio_info sc27xx_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .read_raw = &sc27xx_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .write_raw = &sc27xx_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SC27XX_ADC_CHANNEL(index, mask) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .channel = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .datasheet_name = "CH##index", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct iio_chan_spec sc27xx_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Enable ADC work clock and controller clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto disable_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* ADC channel scales' calibration from nvmem device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = sc27xx_adc_scale_calibration(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = sc27xx_adc_scale_calibration(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) disable_adc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SC27XX_MODULE_ADC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void sc27xx_adc_disable(void *_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sc27xx_adc_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Disable ADC work clock and controller clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SC27XX_MODULE_ADC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int sc27xx_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct sc27xx_adc_data *sc27xx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sc27xx_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!sc27xx_data->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(dev, "failed to get ADC regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(dev, "failed to get ADC base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) sc27xx_data->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (sc27xx_data->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return sc27xx_data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = of_hwspin_lock_get_id(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(dev, "failed to get hwspinlock id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!sc27xx_data->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(dev, "failed to request hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) sc27xx_data->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = sc27xx_adc_enable(sc27xx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(dev, "failed to enable ADC module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(dev, "failed to add ADC disable action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) indio_dev->info = &sc27xx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) indio_dev->channels = sc27xx_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_err(dev, "could not register iio (ADC)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct of_device_id sc27xx_adc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { .compatible = "sprd,sc2731-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct platform_driver sc27xx_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .probe = sc27xx_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "sc27xx-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .of_match_table = sc27xx_adc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_platform_driver(sc27xx_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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