^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip Successive Approximation Register (SAR) A/D Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SARADC_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SARADC_STAS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SARADC_STAS_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SARADC_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SARADC_CTRL_IRQ_STATUS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SARADC_CTRL_IRQ_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SARADC_CTRL_POWER_CTRL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SARADC_CTRL_CHN_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SARADC_DLY_PU_SOC 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SARADC_DLY_PU_SOC_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SARADC_TIMEOUT msecs_to_jiffies(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SARADC_MAX_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* v2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SARADC2_CONV_CON 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SARADC_T_PD_SOC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SARADC_T_DAS_SOC 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SARADC2_END_INT_EN 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SARADC2_ST_CON 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SARADC2_STATUS 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SARADC2_END_INT_ST 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SARADC2_DATA_BASE 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SARADC2_EN_END_INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SARADC2_START BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SARADC2_SINGLE_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct rockchip_saradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct rockchip_saradc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void (*start)(struct rockchip_saradc *info, int chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int (*read)(struct rockchip_saradc *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void (*power_down)(struct rockchip_saradc *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct rockchip_saradc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int uv_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct rockchip_saradc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 last_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct iio_chan_spec *last_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void rockchip_saradc_reset_controller(struct reset_control *reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void rockchip_saradc_start_v1(struct rockchip_saradc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* 8 clock periods as delay between power up and start cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Select the channel to be used and trigger conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void rockchip_saradc_start_v2(struct rockchip_saradc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* If read other chn at anytime, then chn1 will error, assert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * controller as a workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (info->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rockchip_saradc_reset_controller(info->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void rockchip_saradc_start(struct rockchip_saradc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) info->data->start(info, chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return readl_relaxed(info->regs + SARADC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) channel = info->chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) channel = info->last_chan->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) offset = SARADC2_DATA_BASE + channel * 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return readl_relaxed(info->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int rockchip_saradc_read(struct rockchip_saradc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return info->data->read(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel_relaxed(0, info->regs + SARADC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void rockchip_saradc_power_down(struct rockchip_saradc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (info->data->power_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) info->data->power_down(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int rockchip_saradc_conversion(struct rockchip_saradc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct iio_chan_spec const *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* prevent isr get NULL last_chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) info->last_chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rockchip_saradc_start(info, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct rockchip_saradc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (info->test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (info->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = rockchip_saradc_conversion(info, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rockchip_saradc_power_down(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *val = info->last_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* It is a dummy regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (info->uv_vref < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return info->uv_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *val = info->uv_vref / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct rockchip_saradc *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) info->last_val = rockchip_saradc_read(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifndef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) rockchip_saradc_power_down(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_lock_irqsave(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (info->test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_info("chn[%d] val = %d\n", info->chn, info->last_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mod_delayed_work(info->wq, &info->work, msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct iio_info rockchip_saradc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .read_raw = rockchip_saradc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SARADC_CHANNEL(_index, _id, _res) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .channel = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .datasheet_name = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .scan_index = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .realbits = _res, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SARADC_CHANNEL(0, "adc0", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SARADC_CHANNEL(1, "adc1", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SARADC_CHANNEL(2, "adc2", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct rockchip_saradc_data saradc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .channels = rockchip_saradc_iio_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .clk_rate = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .start = rockchip_saradc_start_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .read = rockchip_saradc_read_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .power_down = rockchip_saradc_power_down_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SARADC_CHANNEL(0, "adc0", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SARADC_CHANNEL(1, "adc1", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct rockchip_saradc_data rk3066_tsadc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .channels = rockchip_rk3066_tsadc_iio_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .clk_rate = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .start = rockchip_saradc_start_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .read = rockchip_saradc_read_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .power_down = rockchip_saradc_power_down_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SARADC_CHANNEL(0, "adc0", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SARADC_CHANNEL(1, "adc1", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SARADC_CHANNEL(2, "adc2", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SARADC_CHANNEL(3, "adc3", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SARADC_CHANNEL(4, "adc4", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SARADC_CHANNEL(5, "adc5", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct rockchip_saradc_data rk3399_saradc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .channels = rockchip_rk3399_saradc_iio_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .clk_rate = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .start = rockchip_saradc_start_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .read = rockchip_saradc_read_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .power_down = rockchip_saradc_power_down_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SARADC_CHANNEL(0, "adc0", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SARADC_CHANNEL(1, "adc1", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SARADC_CHANNEL(2, "adc2", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SARADC_CHANNEL(3, "adc3", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SARADC_CHANNEL(4, "adc4", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SARADC_CHANNEL(5, "adc5", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SARADC_CHANNEL(6, "adc6", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SARADC_CHANNEL(7, "adc7", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct rockchip_saradc_data rk3568_saradc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .channels = rockchip_rk3568_saradc_iio_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .clk_rate = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .start = rockchip_saradc_start_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .read = rockchip_saradc_read_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .power_down = rockchip_saradc_power_down_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SARADC_CHANNEL(0, "adc0", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SARADC_CHANNEL(1, "adc1", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SARADC_CHANNEL(2, "adc2", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SARADC_CHANNEL(3, "adc3", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SARADC_CHANNEL(4, "adc4", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SARADC_CHANNEL(5, "adc5", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SARADC_CHANNEL(6, "adc6", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SARADC_CHANNEL(7, "adc7", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct rockchip_saradc_data rk3588_saradc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .channels = rockchip_rk3588_saradc_iio_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .clk_rate = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .start = rockchip_saradc_start_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .read = rockchip_saradc_read_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct iio_chan_spec rockchip_rv1106_saradc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SARADC_CHANNEL(0, "adc0", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SARADC_CHANNEL(1, "adc1", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct rockchip_saradc_data rv1106_saradc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .channels = rockchip_rv1106_saradc_iio_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .num_channels = ARRAY_SIZE(rockchip_rv1106_saradc_iio_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .clk_rate = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .start = rockchip_saradc_start_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .read = rockchip_saradc_read_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct of_device_id rockchip_saradc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .compatible = "rockchip,saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .data = &saradc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .compatible = "rockchip,rk3066-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .data = &rk3066_tsadc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .compatible = "rockchip,rk3399-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .data = &rk3399_saradc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .compatible = "rockchip,rk3568-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .data = &rk3568_saradc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .compatible = "rockchip,rk3588-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .data = &rk3588_saradc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .compatible = "rockchip,rv1106-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .data = &rv1106_saradc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Reset SARADC Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void rockchip_saradc_reset_controller(struct reset_control *reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reset_control_assert(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reset_control_deassert(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void rockchip_saradc_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct rockchip_saradc *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void rockchip_saradc_pclk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct rockchip_saradc *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_disable_unprepare(info->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void rockchip_saradc_regulator_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct rockchip_saradc *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct iio_dev *i_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct rockchip_saradc *info = iio_priv(i_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @values: each channel takes an u16 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @timestamp: will be 8-byte aligned automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u16 values[SARADC_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int i, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mutex_lock(&i_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct iio_chan_spec *chan = &i_dev->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = rockchip_saradc_conversion(info, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) rockchip_saradc_power_down(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) data.values[j] = info->last_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mutex_unlock(&i_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) iio_trigger_notify_done(i_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static ssize_t saradc_test_chn_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) const char *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct rockchip_saradc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err = kstrtou32(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spin_lock_irqsave(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (val > SARADC_CTRL_CHN_MASK && info->test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) info->test = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cancel_delayed_work_sync(&info->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!info->test && val < SARADC_CTRL_CHN_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) info->test = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) info->chn = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mod_delayed_work(info->wq, &info->work, msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spin_unlock_irqrestore(&info->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static DEVICE_ATTR_WO(saradc_test_chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct attribute *saradc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &dev_attr_saradc_test_chn.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct attribute_group rockchip_saradc_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .attrs = saradc_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void rockchip_saradc_remove_sysgroup(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct platform_device *pdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sysfs_remove_group(&pdev->dev.kobj, &rockchip_saradc_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void rockchip_saradc_destroy_wq(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct rockchip_saradc *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) destroy_workqueue(info->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void rockchip_saradc_test_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct rockchip_saradc *info = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct rockchip_saradc, work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) rockchip_saradc_start(info, info->chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int rockchip_saradc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct rockchip_saradc *info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct iio_dev *indio_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_err(&pdev->dev, "failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) match = of_match_device(rockchip_saradc_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(&pdev->dev, "failed to match device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) info->data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Sanity check for possible later IP variants with more channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (info->data->num_channels > SARADC_MAX_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(&pdev->dev, "max channels exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) info->regs = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(info->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return PTR_ERR(info->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * The reset should be an optional property, as it should work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * with old devicetrees as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) info->reset = devm_reset_control_get_exclusive(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "saradc-apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (IS_ERR(info->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = PTR_ERR(info->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret != -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_dbg(&pdev->dev, "no reset control found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) info->reset = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) init_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0, dev_name(&pdev->dev), info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (IS_ERR(info->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(&pdev->dev, "failed to get pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return PTR_ERR(info->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) info->clk = devm_clk_get(&pdev->dev, "saradc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(&pdev->dev, "failed to get adc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) info->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (IS_ERR(info->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_err(&pdev->dev, "failed to get regulator, %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PTR_ERR(info->vref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return PTR_ERR(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (info->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rockchip_saradc_reset_controller(info->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Use a default value for the converter clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * This may become user-configurable in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = clk_set_rate(info->clk, info->data->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = regulator_enable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_err(&pdev->dev, "failed to enable vref regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rockchip_saradc_regulator_disable, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(&pdev->dev, "failed to register devm action, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) info->uv_vref = regulator_get_voltage(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (info->uv_vref < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_err(&pdev->dev, "failed to get voltage\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = info->uv_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = clk_prepare_enable(info->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(&pdev->dev, "failed to enable pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rockchip_saradc_pclk_disable, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_err(&pdev->dev, "failed to register devm action, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(&pdev->dev, "failed to enable converter clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rockchip_saradc_clk_disable, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(&pdev->dev, "failed to register devm action, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) indio_dev->info = &rockchip_saradc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) indio_dev->channels = info->data->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) indio_dev->num_channels = info->data->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) rockchip_saradc_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) info->wq = create_singlethread_workqueue("adc_wq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) INIT_DELAYED_WORK(&info->work, rockchip_saradc_test_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) spin_lock_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = sysfs_create_group(&pdev->dev.kobj, &rockchip_saradc_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) rockchip_saradc_remove_sysgroup, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(&pdev->dev, "failed to register devm action, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rockchip_saradc_destroy_wq, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(&pdev->dev, "failed to register destroy_wq, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return devm_iio_device_register(&pdev->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int rockchip_saradc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct rockchip_saradc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Avoid reading saradc when suspending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) clk_disable_unprepare(info->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) info->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int rockchip_saradc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct rockchip_saradc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = regulator_enable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = clk_prepare_enable(info->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) clk_disable_unprepare(info->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) info->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rockchip_saradc_suspend, rockchip_saradc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static struct platform_driver rockchip_saradc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .probe = rockchip_saradc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .name = "rockchip-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .of_match_table = rockchip_saradc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .pm = &rockchip_saradc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) module_platform_driver(rockchip_saradc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) MODULE_DESCRIPTION("Rockchip SARADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags