^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm PM8xxx PMIC XOADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * These ADCs are known as HK/XO (house keeping / chrystal oscillator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * "XO" in "XOADC" means Chrystal Oscillator. It's a bunch of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * specific-purpose and general purpose ADC converters and channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "qcom-vadc-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Definitions for the "user processor" registers lifted from the v3.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * drivers/misc/pmic8058-xoadc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * drivers/hwmon/pm8xxx-adc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * None of them contain any complete register specification, so this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * a best effort of combining the information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* These appear to be "battery monitor" registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADC_ARB_BTM_CNTRL1 0x17e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADC_ARB_BTM_CNTRL1_EOC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADC_ARB_BTM_CNTRL1_REQ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADC_ARB_BTM_AMUX_CNTRL 0x17f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADC_ARB_BTM_ANA_PARAM 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADC_ARB_BTM_DIG_PARAM 0x181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADC_ARB_BTM_RSV 0x182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADC_ARB_BTM_DATA1 0x183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADC_ARB_BTM_DATA0 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADC_ARB_BTM_BAT_COOL_THR1 0x185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADC_ARB_BTM_BAT_COOL_THR0 0x186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADC_ARB_BTM_BAT_WARM_THR1 0x187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADC_ARB_BTM_BAT_WARM_THR0 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADC_ARB_BTM_CNTRL2 0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Proper ADC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADC_ARB_USRP_CNTRL 0x197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADC_ARB_USRP_CNTRL_EN_ARB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADC_ARB_USRP_CNTRL_RSV1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADC_ARB_USRP_CNTRL_RSV2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADC_ARB_USRP_CNTRL_RSV3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADC_ARB_USRP_CNTRL_RSV4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADC_ARB_USRP_CNTRL_RSV5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADC_ARB_USRP_CNTRL_EOC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADC_ARB_USRP_CNTRL_REQ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADC_ARB_USRP_AMUX_CNTRL 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * The channel mask includes the bits selecting channel mux and prescaler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * on PM8058, or channel mux and premux on PM8921.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* On PM8058 this is prescaling, on PM8921 this is premux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADC_AMUX_PREMUX_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADC_AMUX_SEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* We know very little about the bits in this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADC_ARB_USRP_ANA_PARAM 0x199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADC_ARB_USRP_ANA_PARAM_DIS 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADC_ARB_USRP_ANA_PARAM_EN 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADC_ARB_USRP_DIG_PARAM 0x19A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * On a later ADC the decimation factors are defined as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 00 = 512, 01 = 1024, 10 = 2048, 11 = 4096 so assume this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * holds also for this older XOADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ADC_DIG_PARAM_DEC_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ADC_ARB_USRP_RSV 0x19B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADC_ARB_USRP_RSV_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADC_ARB_USRP_RSV_DTEST0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADC_ARB_USRP_RSV_DTEST1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADC_ARB_USRP_RSV_OP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ADC_ARB_USRP_RSV_TRM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADC_RSV_IP_SEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ADC_ARB_USRP_DATA0 0x19D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ADC_ARB_USRP_DATA1 0x19C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Physical channels which MUST exist on all PM variants in order to provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * proper reference points for calibration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @PM8XXX_CHANNEL_INTERNAL: 625mV reference channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @PM8XXX_CHANNEL_125V: 1250mV reference channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @PM8XXX_CHANNEL_INTERNAL_2: 325mV reference channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @PM8XXX_CHANNEL_MUXOFF: channel to reduce input load on mux, apparently also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * measures XO temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PM8XXX_CHANNEL_INTERNAL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PM8XXX_CHANNEL_125V 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PM8XXX_CHANNEL_INTERNAL_2 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PM8XXX_CHANNEL_MUXOFF 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * PM8058 AMUX premux scaling, two bits. This is done of the channel before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * reaching the AMUX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PM8058_AMUX_PRESCALE_0 0x0 /* No scaling on the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PM8058_AMUX_PRESCALE_1 0x1 /* Unity scaling selected by the user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PM8058_AMUX_PRESCALE_1_DIV3 0x2 /* 1/3 prescaler on the input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Defines reference voltage for the XOADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AMUX_RSV0 0x0 /* XO_IN/XOADC_GND, special selection to read XO temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AMUX_RSV1 0x1 /* PMIC_IN/XOADC_GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AMUX_RSV2 0x2 /* PMIC_IN/BMS_CSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AMUX_RSV3 0x3 /* not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AMUX_RSV4 0x4 /* XOADC_GND/XOADC_GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AMUX_RSV5 0x5 /* XOADC_VREF/XOADC_GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define XOADC_RSV_MAX 5 /* 3 bits 0..7, 3 and 6,7 are invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * struct xoadc_channel - encodes channel properties and defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @datasheet_name: the hardwarename of this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @pre_scale_mux: prescale (PM8058) or premux (PM8921) for selecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * this channel. Both this and the amux channel is needed to uniquely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * identify a channel. Values 0..3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @amux_channel: value of the ADC_ARB_USRP_AMUX_CNTRL register for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * channel, bits 4..7, selects the amux, values 0..f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @prescale: the channels have hard-coded prescale ratios defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * by the hardware, this tells us what it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @type: corresponding IIO channel type, usually IIO_VOLTAGE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * IIO_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @scale_fn_type: the liner interpolation etc to convert the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * ADC code to the value that IIO expects, in uV or millicelsius
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * etc. This scale function can be pretty elaborate if different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * thermistors are connected or other hardware characteristics are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * deployed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @amux_ip_rsv: ratiometric scale value used by the analog muxer: this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * selects the reference voltage for ratiometric scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct xoadc_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *datasheet_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 pre_scale_mux:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 amux_channel:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const struct vadc_prescale_ratio prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum iio_chan_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum vadc_scale_fn_type scale_fn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 amux_ip_rsv:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * struct xoadc_variant - encodes the XOADC variant characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @name: name of this PMIC variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @channels: the hardware channels and respective settings and defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @broken_ratiometric: if the PMIC has broken ratiometric scaling (this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * is a known problem on PM8058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @prescaling: this variant uses AMUX bits 2 & 3 for prescaling (PM8058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @second_level_mux: this variant uses AMUX bits 2 & 3 for a second level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct xoadc_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const struct xoadc_channel *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bool broken_ratiometric;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool prescaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bool second_level_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * XOADC_CHAN macro parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * _dname: the name of the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * _presmux: prescaler (PM8058) or premux (PM8921) setting for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * _amux: the value in bits 2..7 of the ADC_ARB_USRP_AMUX_CNTRL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * for this channel. On some PMICs some of the bits select a prescaler, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * on some PMICs some of the bits select various complex multiplex settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * _type: IIO channel type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * _prenum: prescaler numerator (dividend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * _preden: prescaler denominator (divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * _scale: scaling function type, this selects how the raw valued is mangled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * to output the actual processed measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * _amip: analog mux input parent when using ratiometric measurements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define XOADC_CHAN(_dname, _presmux, _amux, _type, _prenum, _preden, _scale, _amip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .datasheet_name = __stringify(_dname), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .pre_scale_mux = _presmux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .amux_channel = _amux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .prescale = { .num = _prenum, .den = _preden }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .scale_fn_type = _scale, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .amux_ip_rsv = _amip, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Taken from arch/arm/mach-msm/board-9615.c in the vendor tree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * TODO: incomplete, needs testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct xoadc_channel pm8018_xoadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) XOADC_CHAN(VPH_PWR, 0x00, 0x02, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Used for battery ID or battery temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { }, /* Sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Taken from arch/arm/mach-msm/board-8930-pmic.c in the vendor tree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * TODO: needs testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct xoadc_channel pm8038_xoadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* AMUX8 used for battery temperature in most cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { }, /* Sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * This was created by cross-referencing the vendor tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * arch/arm/mach-msm/board-msm8x60.c msm_adc_channels_data[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * with the "channel types" (first field) to find the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * configuration for these channels on an MSM8x60 i.e. PM8058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct xoadc_channel pm8058_xoadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 10, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * AMUX channels 5 thru 9 are referred to as MPP5 thru MPP9 in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * some code and documentation. But they are really just 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * channels just like any other. They are connected to a switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * matrix where they can be routed to any of the MPPs, not just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * 1-to-1 onto MPP5 thru 9, so naming them MPP5 thru MPP9 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * very confusing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* There are also "unity" and divided by 3 channels (prescaler) but noone is using them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { }, /* Sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * The PM8921 has some pre-muxing on its channels, this comes from the vendor tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * include/linux/mfd/pm8xxx/pm8xxx-adc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * board-flo-pmic.c (Nexus 7) and board-8064-pmic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct xoadc_channel pm8921_xoadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* channel "ICHG" is reserved and not used on PM8921 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) XOADC_CHAN(IBAT, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* CHAN 6 & 7 (MPP1 & MPP2) are reserved for MPP channels on PM8921 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) XOADC_CHAN(BATT_THERM, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) XOADC_CHAN(BATT_ID, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* FIXME: look into the scaling of this temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) XOADC_CHAN(CHG_TEMP, 0x00, 0x0e, IIO_TEMP, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* The following channels have premux bit 0 set to 1 (all end in 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) XOADC_CHAN(ATEST_8, 0x01, 0x00, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Set scaling to 1/2 based on the name for these two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) XOADC_CHAN(USB_SNS_DIV20, 0x01, 0x01, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) XOADC_CHAN(DCIN_SNS_DIV20, 0x01, 0x02, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) XOADC_CHAN(AMUX3, 0x01, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) XOADC_CHAN(AMUX4, 0x01, 0x04, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) XOADC_CHAN(AMUX5, 0x01, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) XOADC_CHAN(AMUX6, 0x01, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) XOADC_CHAN(AMUX7, 0x01, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) XOADC_CHAN(AMUX8, 0x01, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Internal test signals, I think */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) XOADC_CHAN(ATEST_1, 0x01, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) XOADC_CHAN(ATEST_2, 0x01, 0x0a, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) XOADC_CHAN(ATEST_3, 0x01, 0x0b, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) XOADC_CHAN(ATEST_4, 0x01, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) XOADC_CHAN(ATEST_5, 0x01, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) XOADC_CHAN(ATEST_6, 0x01, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) XOADC_CHAN(ATEST_7, 0x01, 0x0f, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* The following channels have premux bit 1 set to 1 (all end in 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* I guess even ATEST8 will be divided by 3 here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) XOADC_CHAN(ATEST_8, 0x02, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* I guess div 2 div 3 becomes div 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) XOADC_CHAN(USB_SNS_DIV20_DIV3, 0x02, 0x01, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) XOADC_CHAN(DCIN_SNS_DIV20_DIV3, 0x02, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) XOADC_CHAN(AMUX3_DIV3, 0x02, 0x03, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) XOADC_CHAN(AMUX4_DIV3, 0x02, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) XOADC_CHAN(AMUX5_DIV3, 0x02, 0x05, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) XOADC_CHAN(AMUX6_DIV3, 0x02, 0x06, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) XOADC_CHAN(AMUX7_DIV3, 0x02, 0x07, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) XOADC_CHAN(AMUX8_DIV3, 0x02, 0x08, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) XOADC_CHAN(ATEST_1_DIV3, 0x02, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) XOADC_CHAN(ATEST_2_DIV3, 0x02, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) XOADC_CHAN(ATEST_3_DIV3, 0x02, 0x0b, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) XOADC_CHAN(ATEST_4_DIV3, 0x02, 0x0c, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) XOADC_CHAN(ATEST_5_DIV3, 0x02, 0x0d, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) XOADC_CHAN(ATEST_6_DIV3, 0x02, 0x0e, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) XOADC_CHAN(ATEST_7_DIV3, 0x02, 0x0f, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { }, /* Sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * struct pm8xxx_chan_info - ADC channel information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @name: name of this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * @hwchan: pointer to hardware channel information (muxing & scaling settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @calibration: whether to use absolute or ratiometric calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @scale_fn_type: scaling function type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @decimation: 0,1,2,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @amux_ip_rsv: ratiometric scale value if using ratiometric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * calibration: 0, 1, 2, 4, 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct pm8xxx_chan_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct xoadc_channel *hwchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum vadc_calibration calibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 decimation:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 amux_ip_rsv:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * struct pm8xxx_xoadc - state container for the XOADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @map: regmap to access registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @variant: XOADC variant characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * @vref: reference voltage regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * characteristics of the channels, and sensible default settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * @nchans: number of channels, configured by the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * @chans: the channel information per-channel, configured by the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * @iio_chans: IIO channel specifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * @graph: linear calibration parameters for absolute and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * ratiometric measurements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * @complete: completion to indicate end of conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * @lock: lock to restrict access to the hardware to one client at the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct pm8xxx_xoadc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const struct xoadc_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int nchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct pm8xxx_chan_info *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct iio_chan_spec *iio_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct vadc_linear_graph graph[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static irqreturn_t pm8xxx_eoc_irq(int irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct iio_dev *indio_dev = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) complete(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct pm8xxx_chan_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pm8xxx_get_channel(struct pm8xxx_xoadc *adc, u8 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) for (i = 0; i < adc->nchans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct pm8xxx_chan_info *ch = &adc->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ch->hwchan->amux_channel == chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const struct pm8xxx_chan_info *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 rsv, u16 *adc_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) bool force_ratiometric)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 rsvmask, rsvval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 lsb, msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Mux in this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Set up ratiometric scale value, mask off all bits except these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (adc->variant->broken_ratiometric && !force_ratiometric) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Apparently the PM8058 has some kind of bug which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * reflected in the vendor tree drivers/misc/pmix8058-xoadc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * which just hardcodes the RSV selector to SEL1 (0x20) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * most cases and SEL0 (0x10) for the MUXOFF channel only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * If we force ratiometric (currently only done when attempting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * to do ratiometric calibration) this doesn't seem to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * very well and I suspect ratiometric conversion is simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * broken or not supported on the PM8058.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * the mode alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Some PM8058 register documentation would be nice to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * this right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) rsvval = ADC_ARB_USRP_RSV_IP_SEL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rsvval = ADC_ARB_USRP_RSV_IP_SEL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (rsv == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ADC_ARB_USRP_RSV_TRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ADC_ARB_USRP_RSV_TRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = regmap_update_bits(adc->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ADC_ARB_USRP_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ~rsvmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rsvval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ADC_ARB_USRP_ANA_PARAM_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Decimation factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ch->decimation << ADC_DIG_PARAM_DEC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ADC_ARB_USRP_ANA_PARAM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Enable the arbiter, the Qualcomm code does it twice like this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ADC_ARB_USRP_CNTRL_EN_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ADC_ARB_USRP_CNTRL_EN_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Fire a request! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) reinit_completion(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ADC_ARB_USRP_CNTRL_EN_ARB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ADC_ARB_USRP_CNTRL_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Next the interrupt occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = wait_for_completion_timeout(&adc->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) VADC_CONV_TIME_MAX_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(adc->dev, "conversion timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) lsb = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) msb = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *adc_code = (msb << 8) | lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Turn off the ADC by setting the arbiter to 0 twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int pm8xxx_read_channel(struct pm8xxx_xoadc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) const struct pm8xxx_chan_info *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u16 *adc_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Normally we just use the ratiometric scale value (RSV) predefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * for the channel, but during calibration we need to modify this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * so this wrapper is a helper hiding the more complex version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return pm8xxx_read_channel_rsv(adc, ch, 0xff, adc_code, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const struct pm8xxx_chan_info *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u16 read_1250v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u16 read_0625v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u16 read_nomux_rsv5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 read_nomux_rsv4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) adc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) adc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Common reference channel calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = pm8xxx_read_channel(adc, ch, &read_1250v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(adc->dev, "could not read 1.25V reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = pm8xxx_read_channel(adc, ch, &read_0625v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_err(adc->dev, "could not read 0.625V reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (read_1250v == read_0625v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(adc->dev, "read same ADC code for 1.25V and 0.625V\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) adc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) adc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_info(adc->dev, "absolute calibration dx = %d uV, dy = %d units\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Ratiometric calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &read_nomux_rsv5, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_err(adc->dev, "could not read MUXOFF reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &read_nomux_rsv4, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(adc->dev, "could not read MUXOFF reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) adc->graph[VADC_CALIB_RATIOMETRIC].dy =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) read_nomux_rsv5 - read_nomux_rsv4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) adc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_info(adc->dev, "ratiometric calibration dx = %d, dy = %d units\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) VADC_RATIOMETRIC_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) adc->graph[VADC_CALIB_RATIOMETRIC].dy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int pm8xxx_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const struct pm8xxx_chan_info *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u16 adc_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ch = pm8xxx_get_channel(adc, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_err(adc->dev, "no such channel %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = pm8xxx_read_channel(adc, ch, &adc_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = qcom_vadc_scale(ch->hwchan->scale_fn_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &adc->graph[ch->calibration],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) &ch->hwchan->prescale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) (ch->calibration == VADC_CALIB_ABSOLUTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) adc_code, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ch = pm8xxx_get_channel(adc, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(adc->dev, "no such channel %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = pm8xxx_read_channel(adc, ch, &adc_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *val = (int)adc_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int pm8xxx_of_xlate(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const struct of_phandle_args *iiospec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u8 pre_scale_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u8 amux_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * First cell is prescaler or premux, second cell is analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (iiospec->args_count != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(&indio_dev->dev, "wrong number of arguments for %pOFn need 2 got %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) iiospec->np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) iiospec->args_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pre_scale_mux = (u8)iiospec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) amux_channel = (u8)iiospec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_dbg(&indio_dev->dev, "pre scale/mux: %02x, amux: %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pre_scale_mux, amux_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* We need to match exactly on the prescale/premux and channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i = 0; i < adc->nchans; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (adc->chans[i].hwchan->pre_scale_mux == pre_scale_mux &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) adc->chans[i].hwchan->amux_channel == amux_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const struct iio_info pm8xxx_xoadc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .of_xlate = pm8xxx_of_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .read_raw = pm8xxx_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int pm8xxx_xoadc_parse_channel(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) const struct xoadc_channel *hw_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct iio_chan_spec *iio_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct pm8xxx_chan_info *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) const struct xoadc_channel *hwchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 pre_scale_mux, amux_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 rsv, dec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int chid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = of_property_read_u32_index(np, "reg", 0, &pre_scale_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_err(dev, "invalid pre scale/mux number %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = of_property_read_u32_index(np, "reg", 1, &amux_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_err(dev, "invalid amux channel number %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Find the right channel setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) chid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) hwchan = &hw_channels[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) while (hwchan && hwchan->datasheet_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (hwchan->pre_scale_mux == pre_scale_mux &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) hwchan->amux_channel == amux_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) hwchan++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) chid++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* The sentinel does not have a name assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!hwchan->datasheet_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev_err(dev, "could not locate channel %02x/%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pre_scale_mux, amux_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ch->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ch->hwchan = hwchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Everyone seems to use absolute calibration except in special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ch->calibration = VADC_CALIB_ABSOLUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Everyone seems to use default ("type 2") decimation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ch->decimation = VADC_DEF_DECIMATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!of_property_read_u32(np, "qcom,ratiometric", &rsv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ch->calibration = VADC_CALIB_RATIOMETRIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (rsv > XOADC_RSV_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(dev, "%s too large RSV value %d\n", name, rsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (rsv == AMUX_RSV3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(dev, "%s invalid RSV value %d\n", name, rsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Optional decimation, if omitted we use the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = of_property_read_u32(np, "qcom,decimation", &dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = qcom_vadc_decimation_from_dt(dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev_err(dev, "%s invalid decimation %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) name, dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ch->decimation = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) iio_chan->channel = chid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) iio_chan->address = hwchan->amux_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) iio_chan->datasheet_name = hwchan->datasheet_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) iio_chan->type = hwchan->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* All channels are raw or processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) BIT(IIO_CHAN_INFO_PROCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) iio_chan->indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_dbg(dev, "channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "ref voltage: %d, decimation %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "prescale %d/%d, scale function %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hwchan->pre_scale_mux, hwchan->amux_channel, ch->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ch->amux_ip_rsv, ch->decimation, hwchan->prescale.num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) hwchan->prescale.den, hwchan->scale_fn_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct pm8xxx_chan_info *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) adc->nchans = of_get_available_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!adc->nchans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(adc->dev, "no channel children\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) sizeof(*adc->iio_chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!adc->iio_chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) adc->chans = devm_kcalloc(adc->dev, adc->nchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) sizeof(*adc->chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!adc->chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ch = &adc->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = pm8xxx_xoadc_parse_channel(adc->dev, child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) adc->variant->channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &adc->iio_chans[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Check for required channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_err(adc->dev, "missing 1.25V reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_err(adc->dev, "missing 0.625V reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(adc->dev, "missing MUXOFF reference channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int pm8xxx_xoadc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) const struct xoadc_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct pm8xxx_xoadc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) variant = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) adc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) adc->variant = variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) init_completion(&adc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = pm8xxx_xoadc_parse_channels(adc, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) map = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dev_err(dev, "parent regmap unavailable.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) adc->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Bring up regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) adc->vref = devm_regulator_get(dev, "xoadc-ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (IS_ERR(adc->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_err(dev, "failed to get XOADC VREF regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return PTR_ERR(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = regulator_enable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(dev, "failed to enable XOADC VREF regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pm8xxx_eoc_irq, NULL, 0, variant->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_err(dev, "unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) goto out_disable_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) indio_dev->name = variant->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) indio_dev->info = &pm8xxx_xoadc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) indio_dev->channels = adc->iio_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) indio_dev->num_channels = adc->nchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto out_disable_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = pm8xxx_calibrate_device(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) goto out_unreg_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_info(dev, "%s XOADC driver enabled\n", variant->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) out_unreg_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) out_disable_vref:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int pm8xxx_xoadc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const struct xoadc_variant pm8018_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = "PM8018-XOADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .channels = pm8018_xoadc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const struct xoadc_variant pm8038_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .name = "PM8038-XOADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .channels = pm8038_xoadc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const struct xoadc_variant pm8058_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .name = "PM8058-XOADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .channels = pm8058_xoadc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .broken_ratiometric = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .prescaling = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct xoadc_variant pm8921_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .name = "PM8921-XOADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .channels = pm8921_xoadc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .second_level_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const struct of_device_id pm8xxx_xoadc_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .compatible = "qcom,pm8018-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .data = &pm8018_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .compatible = "qcom,pm8038-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .data = &pm8038_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .compatible = "qcom,pm8058-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .data = &pm8058_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .compatible = "qcom,pm8921-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .data = &pm8921_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) MODULE_DEVICE_TABLE(of, pm8xxx_xoadc_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static struct platform_driver pm8xxx_xoadc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .name = "pm8xxx-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .of_match_table = pm8xxx_xoadc_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .probe = pm8xxx_xoadc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .remove = pm8xxx_xoadc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) module_platform_driver(pm8xxx_xoadc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) MODULE_DESCRIPTION("PM8xxx XOADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) MODULE_ALIAS("platform:pm8xxx-xoadc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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