^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2019 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct npcm_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) bool int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 adc_sample_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk *adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* ADC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NPCM_ADCCON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NPCM_ADCDATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* ADCCON Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NPCM_ADCCON_ADC_INT_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NPCM_ADCCON_REFSEL BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NPCM_ADCCON_ADC_INT_ST BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NPCM_ADCCON_ADC_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NPCM_ADCCON_ADC_RST BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPCM_ADCCON_ADC_CONV BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPCM_ADCCON_CH_MASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPCM_ADCCON_CH(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPCM_ADCCON_DIV_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPCM_ADC_DATA_MASK(x) ((x) & GENMASK(9, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NPCM_ADC_ENABLE (NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* ADC General Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NPCM_RESOLUTION_BITS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NPCM_INT_VREF_MV 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NPCM_ADC_CHAN(ch) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .channel = ch, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct iio_chan_spec npcm_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) NPCM_ADC_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) NPCM_ADC_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NPCM_ADC_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) NPCM_ADC_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) NPCM_ADC_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NPCM_ADC_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) NPCM_ADC_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) NPCM_ADC_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static irqreturn_t npcm_adc_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 regtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct npcm_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regtemp = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iowrite32(regtemp, info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) wake_up_interruptible(&info->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) info->int_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 regtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Select ADC channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) regtemp = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regtemp &= ~NPCM_ADCCON_CH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) info->int_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = wait_event_interruptible_timeout(info->wq, info->int_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) msecs_to_jiffies(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regtemp = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (regtemp & NPCM_ADCCON_ADC_CONV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* if conversion failed - reset ADC module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reset_control_assert(info->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reset_control_deassert(info->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Enable ADC and start conversion module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) iowrite32(NPCM_ADC_ENABLE | NPCM_ADCCON_ADC_CONV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(info->dev, "RESET ADC Complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *val = NPCM_ADC_DATA_MASK(ioread32(info->regs + NPCM_ADCDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int npcm_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct npcm_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = npcm_adc_read(info, val, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(info->dev, "NPCM ADC read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!IS_ERR(info->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) vref_uv = regulator_get_voltage(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *val = vref_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *val = NPCM_INT_VREF_MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *val2 = NPCM_RESOLUTION_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *val = info->adc_sample_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct iio_info npcm_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .read_raw = &npcm_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct of_device_id npcm_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .compatible = "nuvoton,npcm750-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_DEVICE_TABLE(of, npcm_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int npcm_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 reg_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct npcm_adc *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) info->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (IS_ERR(info->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return PTR_ERR(info->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) info->reset = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (IS_ERR(info->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return PTR_ERR(info->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) info->adc_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (IS_ERR(info->adc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_warn(&pdev->dev, "ADC clock failed: can't read clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return PTR_ERR(info->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* calculate ADC clock sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reg_con = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) div = reg_con & NPCM_ADCCON_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) div = div >> NPCM_ADCCON_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) info->adc_sample_hz = clk_get_rate(info->adc_clk) / ((div + 1) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = devm_request_irq(&pdev->dev, irq, npcm_adc_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "NPCM_ADC", indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "failed requesting interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg_con = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) info->vref = devm_regulator_get_optional(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!IS_ERR(info->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = regulator_enable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(&pdev->dev, "Can't enable ADC reference voltage\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) iowrite32(reg_con & ~NPCM_ADCCON_REFSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Any error which is not ENODEV indicates the regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * has been specified and so is a failure case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (PTR_ERR(info->vref) != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = PTR_ERR(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Use internal reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) iowrite32(reg_con | NPCM_ADCCON_REFSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) init_waitqueue_head(&info->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg_con = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg_con |= NPCM_ADC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Enable the ADC Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) iowrite32(reg_con, info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Start ADC conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) iowrite32(reg_con | NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) indio_dev->info = &npcm_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) indio_dev->channels = npcm_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) indio_dev->num_channels = ARRAY_SIZE(npcm_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(&pdev->dev, "Couldn't register the device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto err_iio_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pr_info("NPCM ADC driver probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err_iio_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) iowrite32(reg_con & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!IS_ERR(info->vref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_disable_unprepare(info->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int npcm_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct npcm_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 regtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regtemp = ioread32(info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) iowrite32(regtemp & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!IS_ERR(info->vref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_disable_unprepare(info->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct platform_driver npcm_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .probe = npcm_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .remove = npcm_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "npcm_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .of_match_table = npcm_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) module_platform_driver(npcm_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("Nuvoton NPCM ADC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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