^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Nuvoton NAU7802 ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NAU7802_REG_PUCTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NAU7802_PUCTRL_RR(x) (x << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NAU7802_PUCTRL_PUD(x) (x << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NAU7802_PUCTRL_PUA(x) (x << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NAU7802_PUCTRL_PUR(x) (x << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NAU7802_PUCTRL_CS(x) (x << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NAU7802_PUCTRL_CR(x) (x << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NAU7802_PUCTRL_AVDDS(x) (x << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NAU7802_REG_CTRL1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NAU7802_CTRL1_VLDO(x) (x << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NAU7802_CTRL1_GAINS(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NAU7802_CTRL1_GAINS_BITS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NAU7802_REG_CTRL2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NAU7802_CTRL2_CHS(x) (x << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NAU7802_CTRL2_CRS(x) (x << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NAU7802_SAMP_FREQ_320 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NAU7802_REG_ADC_B2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NAU7802_REG_ADC_B1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NAU7802_REG_ADC_B0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NAU7802_REG_ADC_CTRL 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NAU7802_MIN_CONVERSIONS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct nau7802_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) s32 last_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct mutex data_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 conversion_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 min_conversions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 scale_avail[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct completion value_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NAU7802_CHANNEL(chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .channel = (chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .scan_index = (chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) BIT(IIO_CHAN_INFO_SAMP_FREQ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct iio_chan_spec nau7802_chan_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) NAU7802_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) NAU7802_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 10, 10, 10, 320};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static ssize_t nau7802_show_scales(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int i, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) st->scale_avail[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) buf[len-1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct attribute *nau7802_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) &iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct attribute_group nau7802_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .attrs = nau7802_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int nau7802_set_gain(struct nau7802_state *st, int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) st->conversion_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto nau7802_sysfs_set_gain_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (ret & (~NAU7802_CTRL1_GAINS_BITS)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) nau7802_sysfs_set_gain_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int nau7802_read_conversion(struct nau7802_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mutex_lock(&st->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (data < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) goto nau7802_read_conversion_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) st->last_value = data << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (data < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto nau7802_read_conversion_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) st->last_value |= data << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (data < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto nau7802_read_conversion_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) st->last_value |= data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) st->last_value = sign_extend32(st->last_value, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) nau7802_read_conversion_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mutex_unlock(&st->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int nau7802_sync(struct nau7802_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret | NAU7802_PUCTRL_CS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct nau7802_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!(status & NAU7802_PUCTRL_CR_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (nau7802_read_conversion(st) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Because there is actually only one ADC for both channels, we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * wait for enough conversions to happen before getting a significant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * value when changing channels and the values are far apart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) st->conversion_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) complete(&st->value_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int nau7802_read_irq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct nau7802_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reinit_completion(&st->value_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enable_irq(st->client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) nau7802_sync(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* read registers to ensure we flush everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = nau7802_read_conversion(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) goto read_chan_info_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Wait for a conversion to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = wait_for_completion_interruptible_timeout(&st->value_ok,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto read_chan_info_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) disable_irq(st->client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *val = st->last_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) read_chan_info_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) disable_irq(st->client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int nau7802_read_poll(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct nau7802_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) nau7802_sync(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* read registers to ensure we flush everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = nau7802_read_conversion(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Because there is actually only one ADC for both channels, we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * wait for enough conversions to happen before getting a significant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * value when changing channels and the values are far appart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (st->sample_rate != NAU7802_SAMP_FREQ_320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mdelay(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = i2c_smbus_read_byte_data(st->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NAU7802_REG_PUCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = nau7802_read_conversion(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) st->conversion_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *val = st->last_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int nau7802_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct nau7802_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Select the channel to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * - Channel 1 is value 0 in the CHS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * - Channel 2 is value 1 in the CHS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (!(ret & NAU7802_CTRL2_CHS_BIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) chan->channel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) st->conversion_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = i2c_smbus_write_byte_data(st->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) NAU7802_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) NAU7802_CTRL2_CHS(chan->channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) NAU7802_CTRL2_CRS(st->sample_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (st->client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = nau7802_read_irq(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = nau7802_read_poll(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * We have 24 bits of signed data, that means 23 bits of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * plus the sign bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *val = st->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *val = nau7802_sample_freq_avail[st->sample_rate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int nau7802_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct nau7802_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (val2 == st->scale_avail[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return nau7802_set_gain(st, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (val == nau7802_sample_freq_avail[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) st->sample_rate = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) st->conversion_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = i2c_smbus_write_byte_data(st->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) NAU7802_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) NAU7802_CTRL2_CRS(st->sample_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct iio_info nau7802_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .read_raw = &nau7802_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .write_raw = &nau7802_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .write_raw_get_fmt = nau7802_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .attrs = &nau7802_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int nau7802_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct nau7802_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(&client->dev, "No device tree node available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) indio_dev->name = dev_name(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) indio_dev->info = &nau7802_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) st->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Reset the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) NAU7802_PUCTRL_RR_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Enter normal operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) NAU7802_PUCTRL_PUD_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * After about 200 usecs, the device should be ready and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * the Power Up bit will be set to 1. If not, wait for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) udelay(210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!(ret & NAU7802_PUCTRL_PUR_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) of_property_read_u32(np, "nuvoton,vldo", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) st->vref_mv = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) NAU7802_PUCTRL_CS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (tmp >= 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) data |= NAU7802_PUCTRL_AVDDS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (tmp >= 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Populate available ADC input ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) >> (23 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) init_completion(&st->value_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * The ADC fires continuously and we can't do anything about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * it. So we need to have the IRQ disabled by default, and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * will enable them back when we will need them..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = request_threaded_irq(client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) nau7802_eoc_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) client->dev.driver->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * What may happen here is that our IRQ controller is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * not able to get level interrupt but this is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * by this ADC as when going over 40 sample per second,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * the interrupt line may stay high between conversions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * So, we continue no matter what but we switch to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "Failed to allocate IRQ, using polling mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) client->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) disable_irq(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * We are polling, use the fastest sample rate by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) st->sample_rate = NAU7802_SAMP_FREQ_320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) NAU7802_CTRL2_CRS(st->sample_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto error_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Setup the ADC channels available on the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) indio_dev->channels = nau7802_chan_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mutex_init(&st->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(&client->dev, "Couldn't register the device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto error_device_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) error_device_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mutex_destroy(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mutex_destroy(&st->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) error_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int nau7802_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct nau7802_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mutex_destroy(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mutex_destroy(&st->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct i2c_device_id nau7802_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { "nau7802", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const struct of_device_id nau7802_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { .compatible = "nuvoton,nau7802" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static struct i2c_driver nau7802_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .probe = nau7802_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .remove = nau7802_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .id_table = nau7802_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .name = "nau7802",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .of_match_table = nau7802_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) module_i2c_driver(nau7802_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags