^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale MXS LRADC ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012 DENX Software Engineering, GmbH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Marek Vasut <marex@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/mxs-lradc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Make this runtime configurable if necessary. Currently, if the buffered mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * seconds. The result is that the samples arrive every 500mS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LRADC_DELAY_TIMER_PER 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LRADC_DELAY_TIMER_LOOP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VREF_MV_BASE 1850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *mx23_lradc_adc_irq_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "mxs-lradc-channel0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "mxs-lradc-channel1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "mxs-lradc-channel2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "mxs-lradc-channel3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "mxs-lradc-channel4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "mxs-lradc-channel5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char *mx28_lradc_adc_irq_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "mxs-lradc-thresh0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "mxs-lradc-thresh1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "mxs-lradc-channel0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "mxs-lradc-channel1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "mxs-lradc-channel2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "mxs-lradc-channel3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "mxs-lradc-channel4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "mxs-lradc-channel5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "mxs-lradc-button0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "mxs-lradc-button1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [IMX23_LRADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) VREF_MV_BASE, /* CH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) VREF_MV_BASE, /* CH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) VREF_MV_BASE, /* CH2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) VREF_MV_BASE, /* CH3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) VREF_MV_BASE, /* CH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) VREF_MV_BASE, /* CH5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) VREF_MV_BASE * 2, /* CH6 VDDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) VREF_MV_BASE * 4, /* CH7 VBATT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) VREF_MV_BASE, /* CH8 Temp sense 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) VREF_MV_BASE, /* CH9 Temp sense 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) VREF_MV_BASE, /* CH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) VREF_MV_BASE, /* CH11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) VREF_MV_BASE, /* CH12 USB_DP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) VREF_MV_BASE, /* CH13 USB_DN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) VREF_MV_BASE, /* CH14 VBG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) VREF_MV_BASE * 4, /* CH15 VDD5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [IMX28_LRADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) VREF_MV_BASE, /* CH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) VREF_MV_BASE, /* CH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) VREF_MV_BASE, /* CH2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) VREF_MV_BASE, /* CH3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) VREF_MV_BASE, /* CH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) VREF_MV_BASE, /* CH5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) VREF_MV_BASE, /* CH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) VREF_MV_BASE * 4, /* CH7 VBATT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) VREF_MV_BASE, /* CH8 Temp sense 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) VREF_MV_BASE, /* CH9 Temp sense 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) VREF_MV_BASE * 2, /* CH10 VDDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) VREF_MV_BASE, /* CH11 VTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) VREF_MV_BASE * 2, /* CH12 VDDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) VREF_MV_BASE, /* CH13 VDDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) VREF_MV_BASE, /* CH14 VBG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) VREF_MV_BASE * 4, /* CH15 VDD5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum mxs_lradc_divbytwo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MXS_LRADC_DIV_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MXS_LRADC_DIV_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mxs_lradc_scale {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int nano;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mxs_lradc_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mxs_lradc *lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Maximum of 8 channels + 8 byte ts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 buffer[10] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const u32 *vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long is_divided;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Raw I/O operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mxs_lradc_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mxs_lradc *lradc = adc->lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * See if there is no buffered operation in progress. If there is simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * bail out. This can be improved to support both buffered and raw IO at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * the same time, yet the code becomes horribly complicated. Therefore I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * applied KISS principle here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = iio_device_claim_direct_mode(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reinit_completion(&adc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * No buffered operation in progress, map the channel and trigger it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Virtual channel 0 is always used here as the others are always not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * used if doing raw sampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (lradc->soc == IMX28_LRADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Enable / disable the divider per requirement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (test_bit(chan, &adc->is_divided))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Clean the slot's previous content, then set new one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(0, adc->base + LRADC_CH(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Enable the IRQ and start sampling the channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Wait for completion on the channel, 1 second max. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Read the data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) iio_device_release_direct_mode(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret, min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret != IIO_VAL_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret != IIO_VAL_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *val = max - min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct mxs_lradc_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (chan->type == IIO_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return mxs_lradc_adc_read_temp(iio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * From the datasheet, we have to multiply by 1.012 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * divide by 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *val2 = 253000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *val = adc->vref_mv[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *val2 = chan->scan_type.realbits -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) test_bit(chan->channel, &adc->is_divided);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * The calculated value from the ADC is in Kelvin, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * want Celsius for hwmon so the offset is -273.15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * The offset is applied before scaling so it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * actually -213.15 * 4 / 1.012 = -1079.644268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *val = -1079;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *val2 = 644268;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int val, int val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mxs_lradc_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct mxs_lradc_scale *scale_avail =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) adc->scale_avail[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = iio_device_claim_direct_mode(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* divider by two disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clear_bit(chan->channel, &adc->is_divided);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* divider by two enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) set_bit(chan->channel, &adc->is_divided);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) iio_device_release_direct_mode(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct iio_dev *iio = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int i, ch, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ch = iio_attr->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) len += sprintf(buf + len, "%u.%09u ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) adc->scale_avail[ch][i].integer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) adc->scale_avail[ch][i].nano);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) len += sprintf(buf + len, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mxs_lradc_adc_show_scale_avail, NULL, ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static SHOW_SCALE_AVAILABLE_ATTR(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static SHOW_SCALE_AVAILABLE_ATTR(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SHOW_SCALE_AVAILABLE_ATTR(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static SHOW_SCALE_AVAILABLE_ATTR(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static SHOW_SCALE_AVAILABLE_ATTR(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SHOW_SCALE_AVAILABLE_ATTR(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SHOW_SCALE_AVAILABLE_ATTR(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SHOW_SCALE_AVAILABLE_ATTR(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static SHOW_SCALE_AVAILABLE_ATTR(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static SHOW_SCALE_AVAILABLE_ATTR(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SHOW_SCALE_AVAILABLE_ATTR(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static SHOW_SCALE_AVAILABLE_ATTR(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static SHOW_SCALE_AVAILABLE_ATTR(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static SHOW_SCALE_AVAILABLE_ATTR(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct attribute *mxs_lradc_adc_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct attribute_group mxs_lradc_adc_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .attrs = mxs_lradc_adc_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct iio_info mxs_lradc_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .read_raw = mxs_lradc_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .write_raw = mxs_lradc_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .attrs = &mxs_lradc_adc_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* IRQ Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct iio_dev *iio = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct mxs_lradc *lradc = adc->lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long reg = readl(adc->base + LRADC_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!(reg & mxs_lradc_irq_mask(lradc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (iio_buffer_enabled(iio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (reg & lradc->buffer_vchans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) spin_lock_irqsave(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) iio_trigger_poll(iio->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spin_unlock_irqrestore(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) complete(&adc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writel(reg & mxs_lradc_irq_mask(lradc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Trigger handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct iio_dev *iio = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const u32 chan_value = LRADC_CH_ACCUMULATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int i, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) adc->buffer[j] = readl(adc->base + LRADC_CH(j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel(chan_value, adc->base + LRADC_CH(j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) adc->buffer[j] &= LRADC_CH_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) iio_trigger_notify_done(iio->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct iio_dev *iio = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .set_trigger_state = &mxs_lradc_adc_configure_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) iio->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) trig->dev.parent = adc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) iio_trigger_set_drvdata(trig, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) trig->ops = &mxs_lradc_adc_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = iio_trigger_register(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) adc->trig = trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) iio_trigger_unregister(adc->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct mxs_lradc *lradc = adc->lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int chan, ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned long enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 ctrl4_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 ctrl4_clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 ctrl1_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) const u32 chan_value = LRADC_CH_ACCUMULATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (lradc->soc == IMX28_LRADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) writel(lradc->buffer_vchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel(chan_value, adc->base + LRADC_CH(ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bitmap_set(&enable, ofs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ofs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct mxs_lradc *lradc = adc->lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel(lradc->buffer_vchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (lradc->soc == IMX28_LRADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const unsigned long *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct mxs_lradc *lradc = adc->lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int rsvd_chans = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long rsvd_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (lradc->use_touchbutton)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (lradc->use_touchbutton)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rsvd_chans++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (lradc->touchscreen_wire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rsvd_chans += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Test for attempts to map channels with special mode of operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Test for attempts to map more channels then available slots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .preenable = &mxs_lradc_adc_buffer_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .postdisable = &mxs_lradc_adc_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Driver initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MXS_ADC_CHAN(idx, chan_type, name) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .type = (chan_type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .scan_index = (idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .channel = (idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .address = (idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .realbits = LRADC_RESOLUTION, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .storagebits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .datasheet_name = (name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Combined Temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .scan_index = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) BIT(IIO_CHAN_INFO_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .channel = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .datasheet_name = "TEMP_DIE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Hidden channel to keep indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .channel = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Combined Temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .scan_index = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) BIT(IIO_CHAN_INFO_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .channel = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .datasheet_name = "TEMP_DIE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Hidden channel to keep indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .channel = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* The ADC always uses DELAY CHANNEL 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) const u32 adc_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writel(adc_cfg, adc->base + LRADC_DELAY(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * Start internal temperature sensing by clearing bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * after power up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(0, adc->base + LRADC_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel(0, adc->base + LRADC_DELAY(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int mxs_lradc_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct mxs_lradc_adc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct iio_dev *iio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct resource *iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret, irq, virq, i, s, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u64 scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const char **irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Allocate the IIO device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) iio = devm_iio_device_alloc(dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!iio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(dev, "Failed to allocate IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) adc->lradc = lradc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) adc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!adc->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) init_completion(&adc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) spin_lock_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) platform_set_drvdata(pdev, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) iio->name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) iio->dev.of_node = dev->parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) iio->info = &mxs_lradc_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) iio->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) iio->masklength = LRADC_MAX_TOTAL_CHANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (lradc->soc == IMX23_LRADC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) iio->channels = mx23_lradc_chan_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) irq_name = mx23_lradc_adc_irq_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) iio->channels = mx28_lradc_chan_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) irq_name = mx28_lradc_adc_irq_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = stmp_reset_block(adc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) irq = platform_get_irq_byname(pdev, irq_name[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) virq = irq_of_parse_and_map(dev->parent->of_node, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 0, irq_name[i], iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = mxs_lradc_adc_trigger_init(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) goto err_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) &mxs_lradc_adc_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) &mxs_lradc_adc_buffer_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Populate available ADC input ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * [s=0] = optional divider by two disabled (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * [s=1] = optional divider by two enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * The scale is calculated by doing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Vref >> (realbits - s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * which multiplies by two on the second component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * of the array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) (LRADC_RESOLUTION - s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) adc->scale_avail[i][s].nano =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) do_div(scale_uv, 100000000) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) adc->scale_avail[i][s].integer = scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Configure the hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mxs_lradc_adc_hw_init(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Register IIO device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = iio_device_register(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(dev, "Failed to register IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto err_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mxs_lradc_adc_hw_stop(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mxs_lradc_adc_trigger_remove(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) err_trig:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) iio_triggered_buffer_cleanup(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int mxs_lradc_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct iio_dev *iio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct mxs_lradc_adc *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) iio_device_unregister(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mxs_lradc_adc_hw_stop(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mxs_lradc_adc_trigger_remove(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) iio_triggered_buffer_cleanup(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct platform_driver mxs_lradc_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = "mxs-lradc-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .probe = mxs_lradc_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .remove = mxs_lradc_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) module_platform_driver(mxs_lradc_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MODULE_ALIAS("platform:mxs-lradc-adc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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