^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MESON_SAR_ADC_REG0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MESON_SAR_ADC_CHAN_LIST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (GENMASK(2, 0) << ((_chan) * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MESON_SAR_ADC_AVG_CNTL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (16 + ((_chan) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (GENMASK(17, 16) << ((_chan) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (0 + ((_chan) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (GENMASK(1, 0) << ((_chan) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MESON_SAR_ADC_REG3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MESON_SAR_ADC_DELAY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MESON_SAR_ADC_LAST_RD 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MESON_SAR_ADC_FIFO_RD 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MESON_SAR_ADC_AUX_SW 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (8 + (((_chan) - 2) * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MESON_SAR_ADC_CHAN_10_SW 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MESON_SAR_ADC_DELTA_10 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * NOTE: registers from here are undocumented (the vendor Linux kernel driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * and u-boot source served as reference). These only seem to be relevant on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * GXBB and newer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MESON_SAR_ADC_REG11 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MESON_SAR_ADC_REG13 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MESON_SAR_ADC_TEMP_OFFSET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* temperature sensor calibration information in eFuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MESON_SAR_ADC_EFUSE_BYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MESON_HHI_DPLL_TOP_0 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* for use with IIO_VAL_INT_PLUS_MICRO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MILLION 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MESON_SAR_ADC_CHAN(_chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .address = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BIT(IIO_CHAN_INFO_CALIBSCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .datasheet_name = "SAR_ADC_CH"#_chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .type = IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BIT(IIO_CHAN_INFO_CALIBSCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .datasheet_name = "TEMP_SENSOR", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MESON_SAR_ADC_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MESON_SAR_ADC_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MESON_SAR_ADC_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MESON_SAR_ADC_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MESON_SAR_ADC_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MESON_SAR_ADC_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MESON_SAR_ADC_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MESON_SAR_ADC_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MESON_SAR_ADC_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MESON_SAR_ADC_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MESON_SAR_ADC_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MESON_SAR_ADC_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MESON_SAR_ADC_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MESON_SAR_ADC_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MESON_SAR_ADC_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MESON_SAR_ADC_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MESON_SAR_ADC_TEMP_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IIO_CHAN_SOFT_TIMESTAMP(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) enum meson_sar_adc_avg_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) NO_AVERAGING = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MEAN_AVERAGING = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MEDIAN_AVERAGING = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum meson_sar_adc_num_samples {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ONE_SAMPLE = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TWO_SAMPLES = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FOUR_SAMPLES = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EIGHT_SAMPLES = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum meson_sar_adc_chan7_mux_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CHAN7_MUX_VSS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CHAN7_MUX_VDD_DIV4 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CHAN7_MUX_VDD_DIV2 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CHAN7_MUX_VDD = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) CHAN7_MUX_CH7_INPUT = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct meson_sar_adc_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool has_bl30_integration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 bandgap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 temperature_trimming_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int temperature_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int temperature_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct meson_sar_adc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const struct meson_sar_adc_param *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct meson_sar_adc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const struct meson_sar_adc_param *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct clk *clkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct clk *adc_sel_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk *adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct clk_gate clk_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct clk *adc_div_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct clk_divider clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int calibbias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int calibscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct regmap *tsc_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) bool temperature_sensor_calibrated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 temperature_sensor_coefficient;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 temperature_sensor_adc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .max_register = MESON_SAR_ADC_REG13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .max_register = MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* use val_calib = scale * val_raw + offset calibration function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int regval, timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * NOTE: we need a small delay before reading the status, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * the sample engine may not have started internally (which would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * seem to us that sampling is already finished).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (timeout < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int regval, fifo_chan, fifo_val, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if(!wait_for_completion_timeout(&priv->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) count = meson_sar_adc_get_fifo_count(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "ADC FIFO has %d element(s) instead of one\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (fifo_chan != chan->address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "ADC FIFO entry belongs to channel %d instead of %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) fifo_chan, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) fifo_val &= GENMASK(priv->param->resolution - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) enum meson_sar_adc_avg_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) enum meson_sar_adc_num_samples samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int val, address = chan->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * the SAR ADC engine allows sampling multiple channels at the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * time. to keep it simple we're only working with one *internal*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * channel, which starts counting at index 0 (which means: count = 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* map channel index 0 to the channel which we want to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (chan->type == IIO_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_update_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) enum meson_sar_adc_chan7_mux_sel sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reinit_completion(&priv->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MESON_SAR_ADC_REG0_SAMPLING_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MESON_SAR_ADC_REG0_SAMPLING_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MESON_SAR_ADC_REG0_SAMPLING_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MESON_SAR_ADC_REG0_SAMPLING_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* wait until all modules are stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) meson_sar_adc_wait_busy_clear(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int meson_sar_adc_lock(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int val, timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (priv->param->has_bl30_integration) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* prevent BL30 from using the SAR ADC while we are using it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MESON_SAR_ADC_DELAY_KERNEL_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MESON_SAR_ADC_DELAY_KERNEL_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * wait until BL30 releases it's lock (so we can use the SAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (timeout < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (priv->param->has_bl30_integration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* allow BL30 to use the SAR ADC again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int count, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!meson_sar_adc_get_fifo_count(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) enum meson_sar_adc_avg_mode avg_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum meson_sar_adc_num_samples avg_samples,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = meson_sar_adc_lock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* clear the FIFO to make sure we're not reading old values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) meson_sar_adc_clear_fifo(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) meson_sar_adc_enable_channel(indio_dev, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) meson_sar_adc_start_sample_engine(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) meson_sar_adc_stop_sample_engine(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) meson_sar_adc_unlock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_warn(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "failed to read sample for channel %lu: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) chan->address, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ONE_SAMPLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case IIO_CHAN_INFO_AVERAGE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return meson_sar_adc_get_sample(indio_dev, chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MEAN_AVERAGING, EIGHT_SAMPLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (chan->type == IIO_VOLTAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = regulator_get_voltage(priv->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "failed to get vref voltage: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) *val2 = priv->param->resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* SoC specific multiplier and divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *val = priv->param->temperature_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *val2 = priv->param->temperature_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* celsius to millicelsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *val *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *val = priv->calibbias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *val = priv->calibscale / MILLION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *val2 = priv->calibscale % MILLION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) priv->param->temperature_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) priv->param->temperature_multiplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *val -= priv->temperature_sensor_adc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const char *clk_parents[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_name(indio_dev->dev.parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) init.ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) clk_parents[0] = __clk_get_name(priv->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) init.parent_names = clk_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) priv->clk_div.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) priv->clk_div.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &priv->clk_div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (WARN_ON(IS_ERR(priv->adc_div_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return PTR_ERR(priv->adc_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_name(indio_dev->dev.parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) init.ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) clk_parents[0] = __clk_get_name(priv->adc_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) init.parent_names = clk_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) priv->clk_gate.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (WARN_ON(IS_ERR(priv->adc_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return PTR_ERR(priv->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct nvmem_cell *temperature_calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) size_t read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "temperature_calib");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (IS_ERR(temperature_calib)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = PTR_ERR(temperature_calib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * leave the temperature sensor disabled if no calibration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * was passed via nvmem-cells.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return dev_err_probe(indio_dev->dev.parent, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "failed to get temperature_calib cell\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) priv->tsc_regmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "amlogic,hhi-sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (IS_ERR(priv->tsc_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "failed to get amlogic,hhi-sysctrl regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return PTR_ERR(priv->tsc_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) read_len = MESON_SAR_ADC_EFUSE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) buf = nvmem_cell_read(temperature_calib, &read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (IS_ERR(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "failed to read temperature_calib cell\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return PTR_ERR(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "invalid read size of temperature_calib cell\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) trimming_bits = priv->param->temperature_trimming_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) trimming_mask = BIT(trimming_bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) priv->temperature_sensor_calibrated =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) priv->temperature_sensor_adc_val = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) priv->temperature_sensor_adc_val >>= trimming_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int meson_sar_adc_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int regval, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * make sure we start at CH7 input since the other muxes are only used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * for internal calibration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (priv->param->has_bl30_integration) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * leave sampling delay and the input clocks as configured by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * BL30 to make sure BL30 gets the values it expects when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * reading the temperature sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) meson_sar_adc_stop_sample_engine(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * disable this bit as seems to be only relevant for Meson6 (based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * on the vendor driver), which we don't support at the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* disable all channels by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* delay between two samples = (10+1) * 1uS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* delay between two samples = (10+1) * 1uS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (i = 2; i <= 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (priv->temperature_sensor_calibrated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MESON_SAR_ADC_DELTA_10_TS_REVE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MESON_SAR_ADC_DELTA_10_TS_REVE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MESON_SAR_ADC_DELTA_10_TS_REVE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MESON_SAR_ADC_DELTA_10_TS_REVE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * set bits [3:0] of the TSC (temperature sensor coefficient)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * to get the correct values when reading the temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) priv->temperature_sensor_coefficient);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (priv->param->temperature_trimming_bits == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (priv->temperature_sensor_coefficient & BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * bit [4] (the 5th bit when starting to count at 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * of the TSC is located in the HHI register area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) regmap_update_bits(priv->tsc_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) MESON_HHI_DPLL_TOP_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) MESON_HHI_DPLL_TOP_0_TSC_BIT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "failed to set adc parent to clkin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "failed to set adc clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const struct meson_sar_adc_param *param = priv->param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (param->bandgap_reg == MESON_SAR_ADC_REG11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) on_off ? enable_mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = meson_sar_adc_lock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto err_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ret = regulator_enable(priv->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "failed to enable vref regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto err_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = clk_prepare_enable(priv->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto err_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) meson_sar_adc_set_bandgap(indio_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) MESON_SAR_ADC_REG3_ADC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MESON_SAR_ADC_REG3_ADC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = clk_prepare_enable(priv->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto err_adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) meson_sar_adc_unlock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) err_adc_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) MESON_SAR_ADC_REG3_ADC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) meson_sar_adc_set_bandgap(indio_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) clk_disable_unprepare(priv->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) err_core_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) regulator_disable(priv->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err_vref:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) meson_sar_adc_unlock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) err_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = meson_sar_adc_lock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) clk_disable_unprepare(priv->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) MESON_SAR_ADC_REG3_ADC_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) meson_sar_adc_set_bandgap(indio_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) clk_disable_unprepare(priv->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) regulator_disable(priv->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) meson_sar_adc_unlock(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static irqreturn_t meson_sar_adc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unsigned int cnt, threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (cnt < threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) complete(&priv->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int meson_sar_adc_calib(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int ret, nominal0, nominal1, value0, value1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* use points 25% and 75% for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) nominal0 = (1 << priv->param->resolution) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) nominal1 = (1 << priv->param->resolution) * 3 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = meson_sar_adc_get_sample(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) &indio_dev->channels[7],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret = meson_sar_adc_get_sample(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) &indio_dev->channels[7],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (value1 <= value0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) value1 - value0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) MILLION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static const struct iio_info meson_sar_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .read_raw = meson_sar_adc_iio_info_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .has_bl30_integration = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .clock_rate = 1150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .bandgap_reg = MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .regmap_config = &meson_sar_adc_regmap_config_meson8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .resolution = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .temperature_trimming_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .temperature_multiplier = 18 * 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .temperature_divider = 1024 * 10 * 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .has_bl30_integration = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .clock_rate = 1150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .bandgap_reg = MESON_SAR_ADC_DELTA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .regmap_config = &meson_sar_adc_regmap_config_meson8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .resolution = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .temperature_trimming_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .temperature_multiplier = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .temperature_divider = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .has_bl30_integration = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .clock_rate = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .bandgap_reg = MESON_SAR_ADC_REG11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .regmap_config = &meson_sar_adc_regmap_config_gxbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .resolution = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .has_bl30_integration = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .clock_rate = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .bandgap_reg = MESON_SAR_ADC_REG11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .regmap_config = &meson_sar_adc_regmap_config_gxbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .resolution = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .param = &meson_sar_adc_meson8_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .name = "meson-meson8-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .param = &meson_sar_adc_meson8b_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .name = "meson-meson8b-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .param = &meson_sar_adc_meson8b_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .name = "meson-meson8m2-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .param = &meson_sar_adc_gxbb_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .name = "meson-gxbb-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .param = &meson_sar_adc_gxl_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .name = "meson-gxl-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .param = &meson_sar_adc_gxl_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .name = "meson-gxm-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .param = &meson_sar_adc_gxl_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = "meson-axg-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .param = &meson_sar_adc_gxl_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .name = "meson-g12a-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const struct of_device_id meson_sar_adc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .compatible = "amlogic,meson8-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .data = &meson_sar_adc_meson8_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .compatible = "amlogic,meson8b-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .data = &meson_sar_adc_meson8b_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .compatible = "amlogic,meson8m2-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .data = &meson_sar_adc_meson8m2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .compatible = "amlogic,meson-gxbb-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .data = &meson_sar_adc_gxbb_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .compatible = "amlogic,meson-gxl-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .data = &meson_sar_adc_gxl_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .compatible = "amlogic,meson-gxm-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .data = &meson_sar_adc_gxm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .compatible = "amlogic,meson-axg-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .data = &meson_sar_adc_axg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .compatible = "amlogic,meson-g12a-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .data = &meson_sar_adc_g12a_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int meson_sar_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) const struct meson_sar_adc_data *match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct meson_sar_adc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_err(&pdev->dev, "failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) init_completion(&priv->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) match_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!match_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dev_err(&pdev->dev, "failed to get match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) priv->param = match_data->param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) indio_dev->name = match_data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) indio_dev->info = &meson_sar_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) priv->param->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (IS_ERR(priv->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_name(&pdev->dev), indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) priv->clkin = devm_clk_get(&pdev->dev, "clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (IS_ERR(priv->clkin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) dev_err(&pdev->dev, "failed to get clkin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return PTR_ERR(priv->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) priv->core_clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (IS_ERR(priv->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_err(&pdev->dev, "failed to get core clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return PTR_ERR(priv->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (IS_ERR(priv->adc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (PTR_ERR(priv->adc_clk) == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) priv->adc_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_err(&pdev->dev, "failed to get adc clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return PTR_ERR(priv->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (IS_ERR(priv->adc_sel_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) priv->adc_sel_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dev_err(&pdev->dev, "failed to get adc_sel clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return PTR_ERR(priv->adc_sel_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (!priv->adc_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ret = meson_sar_adc_clk_init(indio_dev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) priv->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (IS_ERR(priv->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_err(&pdev->dev, "failed to get vref regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return PTR_ERR(priv->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) priv->calibscale = MILLION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (priv->param->temperature_trimming_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = meson_sar_adc_temp_sensor_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (priv->temperature_sensor_calibrated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) indio_dev->num_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) indio_dev->channels = meson_sar_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) indio_dev->num_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ARRAY_SIZE(meson_sar_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = meson_sar_adc_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = meson_sar_adc_hw_enable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = meson_sar_adc_calib(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dev_warn(&pdev->dev, "calibration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto err_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) err_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) meson_sar_adc_hw_disable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int meson_sar_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return meson_sar_adc_hw_disable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return meson_sar_adc_hw_disable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static int __maybe_unused meson_sar_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return meson_sar_adc_hw_enable(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) meson_sar_adc_suspend, meson_sar_adc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static struct platform_driver meson_sar_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .probe = meson_sar_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .remove = meson_sar_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .name = "meson-saradc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .of_match_table = meson_sar_adc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .pm = &meson_sar_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) module_platform_driver(meson_sar_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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