Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Microchip MCP3911, Two-channel Analog Front End
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MCP3911_REG_CHANNEL0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MCP3911_REG_CHANNEL1		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MCP3911_REG_MOD			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MCP3911_REG_PHASE		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MCP3911_REG_GAIN		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MCP3911_REG_STATUSCOM		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MCP3911_STATUSCOM_CH1_24WIDTH	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MCP3911_STATUSCOM_CH0_24WIDTH	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MCP3911_STATUSCOM_EN_OFFCAL	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MCP3911_STATUSCOM_EN_GAINCAL	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MCP3911_REG_CONFIG		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MCP3911_CONFIG_CLKEXT		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCP3911_CONFIG_VREFEXT		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MCP3911_REG_OFFCAL_CH0		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCP3911_REG_GAINCAL_CH0		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MCP3911_REG_OFFCAL_CH1		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCP3911_REG_GAINCAL_CH1		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MCP3911_REG_VREFCAL		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MCP3911_CHANNEL(x)		(MCP3911_REG_CHANNEL0 + x * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MCP3911_OFFCAL(x)		(MCP3911_REG_OFFCAL_CH0 + x * 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Internal voltage reference in uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MCP3911_INT_VREF_UV		1200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MCP3911_REG_READ(reg, id)	((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MCP3911_REG_WRITE(reg, id)	((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MCP3911_NUM_CHANNELS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct mcp3911 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct clk *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	reg = MCP3911_REG_READ(reg, adc->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ret = spi_write_then_read(adc->spi, &reg, 1, val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	be32_to_cpus(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	*val >>= ((4 - len) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		reg >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	val <<= (3 - len) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	cpu_to_be32s(&val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return spi_write(adc->spi, &val, len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		u32 val, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ret = mcp3911_read(adc, reg, &tmp, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	val |= tmp & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return mcp3911_write(adc, reg, val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int mcp3911_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			    struct iio_chan_spec const *channel, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			    int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct mcp3911 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		ret = mcp3911_read(adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				   MCP3911_CHANNEL(channel->channel), val, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		ret = mcp3911_read(adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				   MCP3911_OFFCAL(channel->channel), val, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (adc->vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			ret = regulator_get_voltage(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					"failed to get vref voltage: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				       ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			*val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			*val = MCP3911_INT_VREF_UV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		*val2 = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		ret = IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int mcp3911_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			    struct iio_chan_spec const *channel, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			    int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct mcp3911 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (val2 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		/* Write offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				    3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		/* Enable offset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				MCP3911_STATUSCOM_EN_OFFCAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				MCP3911_STATUSCOM_EN_OFFCAL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCP3911_CHAN(idx) {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.channel = idx,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			BIT(IIO_CHAN_INFO_OFFSET) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			BIT(IIO_CHAN_INFO_SCALE),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct iio_chan_spec mcp3911_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	MCP3911_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	MCP3911_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct iio_info mcp3911_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.read_raw = mcp3911_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.write_raw = mcp3911_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int mcp3911_config(struct mcp3911 *adc, struct device_node *of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 configreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	of_property_read_u32(of_node, "device-addr", &adc->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (adc->dev_addr > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		dev_err(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			"invalid device address (%i). Must be in range 0-3.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			adc->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &configreg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (adc->vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dev_dbg(&adc->spi->dev, "use external voltage reference\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		configreg |= MCP3911_CONFIG_VREFEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_dbg(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			"use internal voltage reference (1.2V)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		configreg &= ~MCP3911_CONFIG_VREFEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (adc->clki) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		dev_dbg(&adc->spi->dev, "use external clock as clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		configreg |= MCP3911_CONFIG_CLKEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		dev_dbg(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			"use crystal oscillator as clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		configreg &= ~MCP3911_CONFIG_CLKEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return  mcp3911_write(adc, MCP3911_REG_CONFIG, configreg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int mcp3911_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct mcp3911 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (IS_ERR(adc->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		if (PTR_ERR(adc->vref) == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			adc->vref = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			dev_err(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				"failed to get regulator (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				PTR_ERR(adc->vref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			return PTR_ERR(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		ret = regulator_enable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	adc->clki = devm_clk_get(&adc->spi->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (IS_ERR(adc->clki)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (PTR_ERR(adc->clki) == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			adc->clki = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			dev_err(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				"failed to get adc clk (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				PTR_ERR(adc->clki));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			ret = PTR_ERR(adc->clki);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			goto reg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		ret = clk_prepare_enable(adc->clki);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			dev_err(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				"Failed to enable clki: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			goto reg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ret = mcp3911_config(adc, spi->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	indio_dev->info = &mcp3911_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	indio_dev->channels = mcp3911_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	clk_disable_unprepare(adc->clki);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) reg_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (adc->vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int mcp3911_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct mcp3911 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	clk_disable_unprepare(adc->clki);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (adc->vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct of_device_id mcp3911_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ .compatible = "microchip,mcp3911" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct spi_device_id mcp3911_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{ "mcp3911", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_DEVICE_TABLE(spi, mcp3911_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct spi_driver mcp3911_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.name = "mcp3911",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.of_match_table = mcp3911_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.probe = mcp3911_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.remove = mcp3911_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.id_table = mcp3911_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) module_spi_driver(mcp3911_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DESCRIPTION("Microchip Technology MCP3911");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_LICENSE("GPL v2");