Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013, Angelo Compagnucci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *            https://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *            https://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This driver exports the value of analog input voltage to sysfs, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * voltage unit is nV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MCP3422_CHANNEL_MASK	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MCP3422_PGA_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCP3422_SRATE_MASK	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MCP3422_SRATE_240	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MCP3422_SRATE_60	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCP3422_SRATE_15	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MCP3422_SRATE_3	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCP3422_PGA_1	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MCP3422_PGA_2	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MCP3422_PGA_4	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MCP3422_PGA_8	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MCP3422_CONT_SAMPLING	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MCP3422_CHANNEL(config)	(((config) & MCP3422_CHANNEL_MASK) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MCP3422_PGA(config)	((config) & MCP3422_PGA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MCP3422_SAMPLE_RATE(config)	(((config) & MCP3422_SRATE_MASK) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCP3422_CHAN(_index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.channel = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				| BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static const int mcp3422_scales[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ 1000000, 500000, 250000, 125000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ 250000,  125000, 62500,  31250  },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ 62500,   31250,  15625,  7812   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ 15625,   7812,   3906,   1953   } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Constant msleep times for data acquisitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static const int mcp3422_read_times[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	[MCP3422_SRATE_240] = 1000 / 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[MCP3422_SRATE_60] = 1000 / 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	[MCP3422_SRATE_15] = 1000 / 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	[MCP3422_SRATE_3] = 1000 / 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* sample rates to integer conversion table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const int mcp3422_sample_rates[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[MCP3422_SRATE_240] = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[MCP3422_SRATE_60] = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[MCP3422_SRATE_15] = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[MCP3422_SRATE_3] = 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* sample rates to sign extension table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const int mcp3422_sign_extend[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	[MCP3422_SRATE_240] = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	[MCP3422_SRATE_60] = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	[MCP3422_SRATE_15] = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[MCP3422_SRATE_3] = 17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Client data (each client gets its own) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct mcp3422 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u8 pga[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ret = i2c_master_send(adc->i2c, &newconfig, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		adc->config = newconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u8 buf[4] = {0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (sample_rate == MCP3422_SRATE_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		ret = i2c_master_recv(adc->i2c, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		temp = get_unaligned_be24(&buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		*config = buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		ret = i2c_master_recv(adc->i2c, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		temp = get_unaligned_be16(&buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		*config = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	*value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int mcp3422_read_channel(struct mcp3422 *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				struct iio_chan_spec const *channel, int *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 req_channel = channel->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (req_channel != MCP3422_CHANNEL(adc->config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		config = adc->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		config &= ~MCP3422_CHANNEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		config |= MCP3422_CHANNEL_VALUE(req_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		config &= ~MCP3422_PGA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ret = mcp3422_update_config(adc, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ret = mcp3422_read(adc, value, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int mcp3422_read_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			struct iio_chan_spec const *channel, int *val1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct mcp3422 *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 pga		 = MCP3422_PGA(adc->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		err = mcp3422_read_channel(adc, channel, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		*val1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		*val2 = mcp3422_scales[sample_rate][pga];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		*val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int mcp3422_write_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			struct iio_chan_spec const *channel, int val1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct mcp3422 *adc = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u8 config = adc->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u8 req_channel = channel->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u8 sample_rate = MCP3422_SAMPLE_RATE(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (val1 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			if (val2 == mcp3422_scales[sample_rate][i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				adc->pga[req_channel] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				config &= ~MCP3422_CHANNEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				config |= MCP3422_CHANNEL_VALUE(req_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				config &= ~MCP3422_PGA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				return mcp3422_update_config(adc, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		switch (val1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		case 240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			temp = MCP3422_SRATE_240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		case 60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			temp = MCP3422_SRATE_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			temp = MCP3422_SRATE_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			if (adc->id > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			temp = MCP3422_SRATE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		config &= ~MCP3422_CHANNEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		config |= MCP3422_CHANNEL_VALUE(req_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		config &= ~MCP3422_SRATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		config |= MCP3422_SAMPLE_RATE_VALUE(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return mcp3422_update_config(adc, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		struct iio_chan_spec const *chan, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static ssize_t mcp3422_show_samp_freqs(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (adc->id > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return sprintf(buf, "240 60 15\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return sprintf(buf, "240 60 15 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static ssize_t mcp3422_show_scales(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		mcp3422_scales[sample_rate][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		mcp3422_scales[sample_rate][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		mcp3422_scales[sample_rate][2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		mcp3422_scales[sample_rate][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		mcp3422_show_samp_freqs, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		mcp3422_show_scales, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct attribute *mcp3422_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct attribute_group mcp3422_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.attrs = mcp3422_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct iio_chan_spec mcp3421_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	MCP3422_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct iio_chan_spec mcp3422_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	MCP3422_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	MCP3422_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct iio_chan_spec mcp3424_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	MCP3422_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	MCP3422_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	MCP3422_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	MCP3422_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct iio_info mcp3422_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.read_raw = mcp3422_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.write_raw = mcp3422_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.write_raw_get_fmt = mcp3422_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.attrs = &mcp3422_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int mcp3422_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct mcp3422 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	adc->i2c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	adc->id = (u8)(id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	indio_dev->name = dev_name(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	indio_dev->info = &mcp3422_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	switch (adc->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		indio_dev->channels = mcp3421_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		indio_dev->channels = mcp3422_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		indio_dev->channels = mcp3424_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* meaningful default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	config = (MCP3422_CONT_SAMPLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		| MCP3422_CHANNEL_VALUE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		| MCP3422_PGA_VALUE(MCP3422_PGA_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		| MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	err = mcp3422_update_config(adc, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	err = devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct i2c_device_id mcp3422_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	{ "mcp3421", 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	{ "mcp3422", 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	{ "mcp3423", 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ "mcp3424", 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{ "mcp3425", 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{ "mcp3426", 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	{ "mcp3427", 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{ "mcp3428", 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_DEVICE_TABLE(i2c, mcp3422_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct of_device_id mcp3422_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	{ .compatible = "mcp3422" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DEVICE_TABLE(of, mcp3422_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct i2c_driver mcp3422_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		.name = "mcp3422",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.of_match_table = mcp3422_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.probe = mcp3422_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.id_table = mcp3422_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) module_i2c_driver(mcp3422_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_LICENSE("GPL v2");